From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753490AbcIAIhS (ORCPT ); Thu, 1 Sep 2016 04:37:18 -0400 Received: from mailout1.w1.samsung.com ([210.118.77.11]:23598 "EHLO mailout1.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752170AbcIAIhP (ORCPT ); Thu, 1 Sep 2016 04:37:15 -0400 X-AuditID: cbfec7f4-f79cb6d000001359-27-57c7e8b89e97 From: Krzysztof Kozlowski To: javier@osg.samsung.com, Arnd Bergmann , Kukjin Kim , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH 1/2] ARM: dts: exynos: Fix mismatched value for SD4 pull up/down configuration on exynos4210 Date: Thu, 01 Sep 2016 10:37:01 +0200 Message-id: <1472719022-27226-1-git-send-email-k.kozlowski@samsung.com> X-Mailer: git-send-email 1.9.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplluLIzCtJLcpLzFFi42I5/e/4Vd0dL46HG7T/VbD4O+kYu8XGGetZ LeYfOcdq8ebtGiaL1y8MLfofv2a2OH9+A7vFpsfXWC0u75rDZjHj/D4mBy6P378mMXpsWtXJ 5rF5Sb3Hlv677B59W1YxenzeJBfAFsVlk5Kak1mWWqRvl8CVMev9NNaCSVwVt+dtZWlg3MzR xcjBISFgItG4WL6LkRPIFJO4cG89WxcjF4eQwFJGiUc3+tkhnEYmieP9O5hAqtgEjCU2L1/C BmKLCHQwSXTclgCxmQUyJTr3zmUHsYUF8iS27l/CCmKzCKhKnLz0ByzOK+AusaJ1CgvENjmJ k8cms05g5F7AyLCKUTS1NLmgOCk911CvODG3uDQvXS85P3cTIySQvuxgXHzM6hCjAAejEg+v w5tj4UKsiWXFlbmHGCU4mJVEeBmeHw8X4k1JrKxKLcqPLyrNSS0+xCjNwaIkzjt31/sQIYH0 xJLU7NTUgtQimCwTB6dUA+OcYIF5tcK5x53sjHaeOCqs4rBu67v8/i++1XeW+c3cHJHSKtag /o1VUmtne6nL59Sa0yE7G+rufdXKmlh8p+Rf7aHAZju1xHMTTu9+FG8883jqJvGN1ufOvJcp nCbjM6UiQWfBi73zLCavlGq4cJcn6MxXkwfcZwW1V0+fuyTJsYHp+sa9gr+VWIozEg21mIuK EwHuAdyKIAIAAA== Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The pinctrl pull up/down register on exynos4210 is 2-bit wide for each pin and it accepts only values of 0, 1 and 3. The pins sd4-bus-width8 were configured with value of 4. The driver does not validate the value so this overflow effectively set a bit 1 in adjacent pins thus configuring them to pull down. The author's intention was probably to set drive strength of 4x. All other bus-widths pins are configured with pull up and drive strength of 4x. Fix this one with same pattern. Fixes: 87711d8c7c70 ("ARM: dts: Add pinctrl node entries for SAMSUNG EXYNOS4210 SoC") Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi index 8046340e50ac..d9b6d25e4abe 100644 --- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi @@ -649,7 +649,7 @@ sd4_bus8: sd4-bus-width8 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = ; - samsung,pin-pud = <4>; + samsung,pin-pud = ; samsung,pin-drv = ; }; -- 1.9.1