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([2a02:2f04:6302:7700:4510:8c44:3b9e:61ae]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47f85bb5127sm16373400f8f.10.2026.07.23.10.16.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 23 Jul 2026 10:16:52 -0700 (PDT) Message-ID: <14727860-74c2-499e-b59c-f1bff48bb855@tuxon.dev> Date: Thu, 23 Jul 2026 20:16:50 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] PCI: rzg3s: Disable refclk on probe failure To: Prabhakar , Claudiu Beznea , Manivannan Sadhasivam , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar , stable@vger.kernel.org References: <20260715223019.3002237-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20260715223019.3002237-2-prabhakar.mahadev-lad.rj@bp.renesas.com> Content-Language: en-US From: claudiu beznea In-Reply-To: <20260715223019.3002237-2-prabhakar.mahadev-lad.rj@bp.renesas.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 7/16/26 01:30, Prabhakar wrote: > From: Lad Prabhakar > > rzg3s_pcie_host_init_port() enables the PCIe reference clock using > clk_prepare_enable(), but if rzg3s_pcie_probe() subsequently fails, for > example because pci_host_probe() returns an error, the probe error path > only releases the clock handle with clk_put(). > > Balance clk_prepare_enable() by calling clk_disable_unprepare() in the > probe cleanup path before releasing the clock, ensuring the reference > clock is properly disabled on probe failure. > > Fixes: 7ef502fb35b28 ("PCI: Add Renesas RZ/G3S host controller driver") > Cc:stable@vger.kernel.org > Signed-off-by: Lad Prabhakar Reviewed-by: Claudiu Beznea