From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755288AbcIGJpk (ORCPT ); Wed, 7 Sep 2016 05:45:40 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:59477 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750791AbcIGJph (ORCPT ); Wed, 7 Sep 2016 05:45:37 -0400 From: Matt Redfearn To: Ralf Baechle CC: , Matt Redfearn , Arnd Bergmann , Tony Wu , Nikolay Martynov , Masahiro Yamada , Kees Cook , , Qais Yousef , , "Michael S. Tsirkin" , Thomas Gleixner , "Rafael J. Wysocki" , James Hogan , Andrew Morton , Markos Chandras , Adam Buchbinder , "Peter Zijlstra (Intel)" , Paul Burton , Daniel Lezcano Subject: [PATCH v2 00/12] MIPS CPC fixup and CPU Idle for MIPSr6 CPUs Date: Wed, 7 Sep 2016 10:45:08 +0100 Message-ID: <1473241520-14917-1-git-send-email-matt.redfearn@imgtec.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.150.130.83] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This updated series incorporates comments from Peter Zijlstra on v1 around the barriers in pm-cps.c. This series fixes a small issue with the CPC driver when A CM3 is present, where a redundant lock was taken. There are then additions to the pm-cps driver to add support for R6 CPUs such as the I6400, and additionally the CM3 present in the I6400. Finally we enable the cpuidle-cps driver for MIPSr6 CPUs. Applies atop v4.8-rc4 Changes in v2: Update comments on barriers Add new patch to define standard MIPS barrier types Use architecturally standard lightweight sync types rather than selecting CPU specific ones. Matt Redfearn (12): MIPS: CPC: Convert bare 'unsigned' to 'unsigned int' MIPS: CPC: Avoid lock when MIPS CM >= 3 is present MIPS: pm-cps: Change FSB workaround to CPU blacklist MIPS: pm-cps: Update comments on barrier instructions MIPS: Barrier: Add definitions of SYNC stype values MIPS: pm-cps: Use MIPS standard lightweight ordering barrier MIPS: pm-cps: Use MIPS standard completion barrier MIPS: pm-cps: Remove selection of sync types MIPS: pm-cps: Add MIPSr6 CPU support MIPS: pm-cps: Support CM3 changes to Coherence Enable Register MIPS: SMP: Wrap call to mips_cpc_lock_other in mips_cm_lock_other cpuidle: cpuidle-cps: Enable use with MIPSr6 CPUs. arch/mips/include/asm/barrier.h | 96 +++++++++++++++++++++++++++++++++ arch/mips/include/asm/mips-cm.h | 1 + arch/mips/include/asm/pm-cps.h | 6 ++- arch/mips/kernel/mips-cpc.c | 17 ++++-- arch/mips/kernel/pm-cps.c | 115 +++++++++++++++++++--------------------- arch/mips/kernel/smp.c | 2 + drivers/cpuidle/Kconfig.mips | 2 +- drivers/cpuidle/cpuidle-cps.c | 2 +- 8 files changed, 173 insertions(+), 68 deletions(-) -- 2.7.4