From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030203AbcIGJrC (ORCPT ); Wed, 7 Sep 2016 05:47:02 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:65369 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756728AbcIGJpm (ORCPT ); Wed, 7 Sep 2016 05:45:42 -0400 From: Matt Redfearn To: Ralf Baechle CC: , Matt Redfearn , Adam Buchbinder , Masahiro Yamada , , Paul Burton , Markos Chandras , Andrew Morton Subject: [PATCH v2 07/12] MIPS: pm-cps: Use MIPS standard completion barrier Date: Wed, 7 Sep 2016 10:45:15 +0100 Message-ID: <1473241520-14917-8-git-send-email-matt.redfearn@imgtec.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1473241520-14917-1-git-send-email-matt.redfearn@imgtec.com> References: <1473241520-14917-1-git-send-email-matt.redfearn@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.150.130.83] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SYNC type 0 is defined in the MIPS architecture as a completion barrier where all loads/stores in the pipeline before the sync instruction must complete before any loads/stores subsequent to the sync instruction. In places where we require loads / stores be globally completed, use the standard completion sync stype. Signed-off-by: Matt Redfearn Reviewed-by: Paul Burton --- Changes in v2: None arch/mips/kernel/pm-cps.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c index d7037fe00d1c..953ff0db9061 100644 --- a/arch/mips/kernel/pm-cps.c +++ b/arch/mips/kernel/pm-cps.c @@ -315,7 +315,7 @@ static int __init cps_gen_flush_fsb(u32 **pp, struct uasm_label **pl, } /* Barrier ensuring previous cache invalidates are complete */ - uasm_i_sync(pp, stype_memory); + uasm_i_sync(pp, STYPE_SYNC); uasm_i_ehb(pp); /* Check whether the pipeline stalled due to the FSB being full */ @@ -467,7 +467,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state) Index_Writeback_Inv_D, lbl_flushdcache); /* Barrier ensuring previous cache invalidates are complete */ - uasm_i_sync(&p, stype_memory); + uasm_i_sync(&p, STYPE_SYNC); uasm_i_ehb(&p); /* @@ -480,7 +480,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state) uasm_i_lw(&p, t0, 0, r_pcohctl); /* Barrier to ensure write to coherence control is complete */ - uasm_i_sync(&p, stype_intervention); + uasm_i_sync(&p, STYPE_SYNC); uasm_i_ehb(&p); /* Disable coherence */ @@ -526,7 +526,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state) } /* Barrier to ensure write to CPC command is complete */ - uasm_i_sync(&p, stype_memory); + uasm_i_sync(&p, STYPE_SYNC); uasm_i_ehb(&p); } @@ -561,7 +561,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state) uasm_i_lw(&p, t0, 0, r_pcohctl); /* Barrier to ensure write to coherence control is complete */ - uasm_i_sync(&p, stype_memory); + uasm_i_sync(&p, STYPE_SYNC); uasm_i_ehb(&p); if (coupled_coherence && (state == CPS_PM_NC_WAIT)) { -- 2.7.4