From: Keguang Zhang <keguang.zhang@gmail.com>
To: linux-clk@vger.kernel.org, linux-mips@linux-mips.org,
linux-kernel@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Kelvin Cheung <keguang.zhang@gmail.com>
Subject: [PATCH V1 3/3] clk: Loongson1: Make use of GENMASK
Date: Mon, 19 Sep 2016 12:38:56 +0800 [thread overview]
Message-ID: <1474259936-9657-4-git-send-email-keguang.zhang@gmail.com> (raw)
In-Reply-To: <1474259936-9657-1-git-send-email-keguang.zhang@gmail.com>
From: Kelvin Cheung <keguang.zhang@gmail.com>
Make use of GENMASK instead of open coding the equivalent operation,
and update the PLL formula.
Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
---
drivers/clk/loongson1/clk-loongson1b.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/loongson1/clk-loongson1b.c b/drivers/clk/loongson1/clk-loongson1b.c
index 4b3d9d2..f36a97e 100644
--- a/drivers/clk/loongson1/clk-loongson1b.c
+++ b/drivers/clk/loongson1/clk-loongson1b.c
@@ -26,7 +26,7 @@ static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
u32 pll, rate;
pll = __raw_readl(LS1X_CLK_PLL_FREQ);
- rate = 12 + (pll & 0x3f) + (((pll >> 8) & 0x3ff) >> 10);
+ rate = 12 + (pll & GENMASK(5, 0));
rate *= OSC;
rate >>= 1;
--
1.9.1
prev parent reply other threads:[~2016-09-19 4:39 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-19 4:38 [PATCH V1 0/3] Refactor Loongson1 clock Keguang Zhang
2016-09-19 4:38 ` [PATCH V1 1/3] clk: Loongson1: " Keguang Zhang
2016-09-23 21:52 ` Stephen Boyd
2016-09-19 4:38 ` [PATCH V1 2/3] clk: Loongson1: Update clocks of Loongson1B Keguang Zhang
2016-09-19 4:38 ` Keguang Zhang [this message]
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