From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753848AbcITIry (ORCPT ); Tue, 20 Sep 2016 04:47:54 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:14074 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753679AbcITIrt (ORCPT ); Tue, 20 Sep 2016 04:47:49 -0400 From: Matt Redfearn To: Ralf Baechle , Bjorn Andersson , Ohad Ben-Cohen , Thomas Gleixner CC: , , , , Matt Redfearn , Hugh Dickins , Huacai Chen , "David S. Miller" , James Hogan , Paul Burton , Andrew Morton Subject: [PATCH v2 2/6] MIPS: tlb-r4k: If there are wired entries, don't use TLBINVF Date: Tue, 20 Sep 2016 09:47:25 +0100 Message-ID: <1474361249-31064-3-git-send-email-matt.redfearn@imgtec.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1474361249-31064-1-git-send-email-matt.redfearn@imgtec.com> References: <1474361249-31064-1-git-send-email-matt.redfearn@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.150.130.83] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When adding a wired entry to the TLB via add_wired_entry, the tlb is flushed with local_flush_tlb_all, which on CPUs with TLBINV results in the new wired entry being flushed again. Behavior of the TLBINV instruction applies to all applicable TLB entries and is unaffected by the setting of the Wired register. Therefore if the TLB has any wired entries, fall back to iterating over the entries rather than blasting them all using TLBINVF. Signed-off-by: Matt Redfearn --- Changes in v2: None arch/mips/mm/tlb-r4k.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index e8b335c16295..4953c1a8cdfd 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -67,8 +67,11 @@ void local_flush_tlb_all(void) entry = read_c0_wired(); - /* Blast 'em all away. */ - if (cpu_has_tlbinv) { + /* + * Blast 'em all away. + * If there are any wired entries, fall back to iterating + */ + if (cpu_has_tlbinv && !entry) { if (current_cpu_data.tlbsizevtlb) { write_c0_index(0); mtc0_tlbw_hazard(); -- 2.7.4