From: "Fenghua Yu" <fenghua.yu@intel.com>
To: "Thomas Gleixner" <tglx@linutronix.de>
Cc: "H. Peter Anvin" <h.peter.anvin@intel.com>,
"Ingo Molnar" <mingo@elte.hu>, "Tony Luck" <tony.luck@intel.com>,
"Peter Zijlstra" <peterz@infradead.org>,
"Stephane Eranian" <eranian@google.com>,
"Borislav Petkov" <bp@suse.de>,
"Dave Hansen" <dave.hansen@intel.com>,
"Nilay Vaish" <nilayvaish@gmail.com>, "Shaohua Li" <shli@fb.com>,
"David Carrillo-Cisneros" <davidcc@google.com>,
"Ravi V Shankar" <ravi.v.shankar@intel.com>,
"Sai Prakhya" <sai.praneeth.prakhya@intel.com>,
"Vikas Shivappa" <vikas.shivappa@linux.intel.com>,
"linux-kernel" <linux-kernel@vger.kernel.org>,
"x86" <x86@kernel.org>, "Fenghua Yu" <fenghua.yu@intel.com>
Subject: [PATCH v3 02/18] cacheinfo: Introduce cache id
Date: Fri, 7 Oct 2016 19:45:47 -0700 [thread overview]
Message-ID: <1475894763-64683-3-git-send-email-fenghua.yu@intel.com> (raw)
In-Reply-To: <1475894763-64683-1-git-send-email-fenghua.yu@intel.com>
From: Fenghua Yu <fenghua.yu@intel.com>
Cache management software needs a name for each instance of a cache of
a particular type.
The current cacheinfo structure does not provide any information about
the underlying hardware so there is no way to expose it.
Hardware with cache management features provides means (cpuid, enumeration
etc.) to retrieve the hardware id of a particular cache instance. Cache
instances which share hardware have the same hardware id.
Add an 'id' field to struct cacheinfo to store this information. Expose
this information under the /sys/devices/system/cpu/cpu*/cache/index*/
directory as well.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
---
drivers/base/cacheinfo.c | 5 +++++
include/linux/cacheinfo.h | 3 +++
2 files changed, 8 insertions(+)
diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index e9fd32e..2a21c15 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
@@ -233,6 +233,7 @@ static ssize_t file_name##_show(struct device *dev, \
return sprintf(buf, "%u\n", this_leaf->object); \
}
+show_one(id, id);
show_one(level, level);
show_one(coherency_line_size, coherency_line_size);
show_one(number_of_sets, number_of_sets);
@@ -314,6 +315,7 @@ static ssize_t write_policy_show(struct device *dev,
return n;
}
+static DEVICE_ATTR_RO(id);
static DEVICE_ATTR_RO(level);
static DEVICE_ATTR_RO(type);
static DEVICE_ATTR_RO(coherency_line_size);
@@ -327,6 +329,7 @@ static DEVICE_ATTR_RO(shared_cpu_list);
static DEVICE_ATTR_RO(physical_line_partition);
static struct attribute *cache_default_attrs[] = {
+ &dev_attr_id.attr,
&dev_attr_type.attr,
&dev_attr_level.attr,
&dev_attr_shared_cpu_map.attr,
@@ -350,6 +353,8 @@ cache_default_attrs_is_visible(struct kobject *kobj,
const struct cpumask *mask = &this_leaf->shared_cpu_map;
umode_t mode = attr->mode;
+ if ((attr == &dev_attr_id.attr) && this_leaf->attributes & CACHE_ID)
+ return mode;
if ((attr == &dev_attr_type.attr) && this_leaf->type)
return mode;
if ((attr == &dev_attr_level.attr) && this_leaf->level)
diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h
index 2189935..0bcbb67 100644
--- a/include/linux/cacheinfo.h
+++ b/include/linux/cacheinfo.h
@@ -18,6 +18,7 @@ enum cache_type {
/**
* struct cacheinfo - represent a cache leaf node
+ * @id: This cache's id. It is unique among caches with the same (type, level).
* @type: type of the cache - data, inst or unified
* @level: represents the hierarchy in the multi-level cache
* @coherency_line_size: size of each cache line usually representing
@@ -44,6 +45,7 @@ enum cache_type {
* keeping, the remaining members form the core properties of the cache
*/
struct cacheinfo {
+ unsigned int id;
enum cache_type type;
unsigned int level;
unsigned int coherency_line_size;
@@ -61,6 +63,7 @@ struct cacheinfo {
#define CACHE_WRITE_ALLOCATE BIT(3)
#define CACHE_ALLOCATE_POLICY_MASK \
(CACHE_READ_ALLOCATE | CACHE_WRITE_ALLOCATE)
+#define CACHE_ID BIT(4)
struct device_node *of_node;
bool disable_sysfs;
--
2.5.0
next prev parent reply other threads:[~2016-10-07 23:44 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-08 2:45 [PATCH v3 00/18] Intel Cache Allocation Technology Fenghua Yu
2016-10-07 23:54 ` [RFC PATCH 19/18] x86/intel_rdt: Add support for L2 cache allocation Luck, Tony
2016-10-08 2:45 ` [PATCH v3 01/18] Documentation, ABI: Add a document entry for cache id Fenghua Yu
2016-10-08 17:11 ` Nilay Vaish
2016-10-10 16:45 ` Luck, Tony
2016-10-11 16:48 ` Nilay Vaish
2016-10-08 2:45 ` Fenghua Yu [this message]
2016-10-08 17:10 ` [PATCH v3 02/18] cacheinfo: Introduce " Nilay Vaish
2016-10-08 2:45 ` [PATCH v3 03/18] x86, intel_cacheinfo: Enable cache id in x86 Fenghua Yu
2016-10-08 2:45 ` [PATCH v3 04/18] x86/intel_rdt: Feature discovery Fenghua Yu
2016-10-08 17:11 ` Nilay Vaish
2016-10-08 20:54 ` Fenghua Yu
2016-10-08 19:52 ` Borislav Petkov
2016-10-11 16:57 ` Nilay Vaish
2016-10-11 17:03 ` Borislav Petkov
2016-10-10 16:01 ` Dave Hansen
2016-10-10 16:18 ` Borislav Petkov
2016-10-08 2:45 ` [PATCH v3 05/18] Documentation, x86: Documentation for Intel resource allocation user interface Fenghua Yu
2016-10-08 17:12 ` Nilay Vaish
2016-10-08 20:33 ` Fenghua Yu
2016-10-10 17:19 ` Luck, Tony
2016-10-11 17:07 ` Nilay Vaish
2016-10-11 18:04 ` Luck, Tony
2016-10-08 2:45 ` [PATCH v3 06/18] x86/intel_rdt: Add CONFIG, Makefile, and basic initialization Fenghua Yu
2016-10-08 20:57 ` Borislav Petkov
2016-10-08 2:45 ` [PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery Fenghua Yu
2016-10-09 11:41 ` Borislav Petkov
2016-10-09 17:09 ` Fenghua Yu
2016-10-09 16:28 ` Borislav Petkov
2016-10-10 18:55 ` Luck, Tony
2016-10-11 11:12 ` Borislav Petkov
2016-10-11 14:51 ` Luck, Tony
2016-10-08 2:45 ` [PATCH v3 08/18] x86/intel_rdt: Pick up L3 RDT parameters from CPUID Fenghua Yu
2016-10-08 2:45 ` [PATCH v3 09/18] x86/cqm: Move PQR_ASSOC management code into generic code used by both CQM and CAT Fenghua Yu
2016-10-08 2:45 ` [PATCH v3 10/18] x86/intel_rdt: Build structures for each resource based on cache topology Fenghua Yu
2016-10-09 21:57 ` Nilay Vaish
2016-10-08 2:45 ` [PATCH v3 11/18] x86/intel_rdt: Add basic resctrl filesystem support Fenghua Yu
2016-10-09 22:31 ` Nilay Vaish
2016-10-10 23:44 ` Luck, Tony
2016-10-08 2:45 ` [PATCH v3 12/18] x86/intel_rdt: Add "info" files to resctrl file system Fenghua Yu
2016-10-08 2:45 ` [PATCH v3 13/18] x86/intel_rdt: Add mkdir " Fenghua Yu
2016-10-10 17:51 ` Nilay Vaish
2016-10-08 2:45 ` [PATCH v3 14/18] x86/intel_rdt: Add cpus file Fenghua Yu
2016-10-08 2:46 ` [PATCH v3 15/18] x86/intel_rdt: Add tasks files Fenghua Yu
2016-10-08 2:46 ` [PATCH v3 16/18] x86/intel_rdt: Add schemata file Fenghua Yu
2016-10-08 2:46 ` [PATCH v3 17/18] x86/intel_rdt: Add scheduler hook Fenghua Yu
2016-10-08 2:46 ` [PATCH v3 18/18] MAINTAINERS: Add maintainer for Intel RDT resource allocation Fenghua Yu
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