From: Andrew Jeffery <andrew@aj.id.au>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Joel Stanley <joel@jms.id.au>,
Mark Rutland <mark.rutland@arm.com>,
Rob Herring <robh+dt@kernel.org>,
"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
openbmc@lists.ozlabs.org
Subject: Re: [PATCH 0/8] pinctrl: aspeed: Fixes for core and g5, implement remaining pins
Date: Tue, 11 Oct 2016 09:57:35 +1030 [thread overview]
Message-ID: <1476142055.16733.4.camel@aj.id.au> (raw)
In-Reply-To: <CACRpkdZWbx1_SYJMOn40teQaEw1JAq80kDAp7N+OYaMRRO6NBg@mail.gmail.com>
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On Mon, 2016-10-10 at 09:59 +0200, Linus Walleij wrote:
> On Tue, Sep 27, 2016 at 4:50 PM, Andrew Jeffery <andrew@aj.id.au> wrote:
>
> >
> > The initial Aspeed pinctrl patches implemented a subset of pins for each of the
> > g4 and g5 SoCs. This series provides a number of fixes to the initial patches,
> > mostly for issues identified in the g5 driver. The fixes account for the first
> > half of the series (up to and including "pinctrl: aspeed-g5: Fix pin
> > association of SPI1 function") and should be applied for 4.9.
> Those are applied for fixes.
Thanks!
>
> >
> > The second half, from "pinctrl: aspeed: Enable capture of off-SCU pinmux
> > state", implements some additional functionality in the core engine for the
> > Aspeed SoCs and follows up with patches implementing mux configuration tables
> > for all remaining pins. Given the significant additions in the last few
> > patches, their lateness in the cycle and the light testing they have received
> > they are best left for 4.10, but I'm keen to get them out for review.
> I'm holding these back until v4.9-rc1 is out.
No worries; they need some discussion when you have the time.
Cheers,
Andrew
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prev parent reply other threads:[~2016-10-10 23:36 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-27 14:50 Andrew Jeffery
2016-09-27 14:50 ` [PATCH 1/8] pinctrl: aspeed: "Not enabled" is a significant mux state Andrew Jeffery
2016-09-29 0:54 ` Joel Stanley
2016-10-10 7:55 ` Linus Walleij
2016-09-27 14:50 ` [PATCH 2/8] pinctrl: aspeed-g5: Fix names of GPID2 pins Andrew Jeffery
2016-09-29 0:54 ` Joel Stanley
2016-10-10 7:56 ` Linus Walleij
2016-09-27 14:50 ` [PATCH 3/8] pinctrl: aspeed-g5: Fix GPIOE1 typo Andrew Jeffery
2016-09-29 0:54 ` Joel Stanley
2016-10-10 7:57 ` Linus Walleij
2016-09-27 14:50 ` [PATCH 4/8] pinctrl: aspeed-g5: Fix pin association of SPI1 function Andrew Jeffery
2016-09-29 0:54 ` Joel Stanley
2016-10-03 18:57 ` Rob Herring
2016-10-10 7:59 ` Linus Walleij
2016-09-27 14:50 ` [PATCH 5/8] pinctrl: aspeed: Enable capture of off-SCU pinmux state Andrew Jeffery
2016-09-29 6:45 ` Joel Stanley
2016-09-29 7:54 ` Andrew Jeffery
2016-10-23 22:20 ` Linus Walleij
2016-10-24 0:29 ` Andrew Jeffery
2016-09-27 14:50 ` [PATCH 6/8] pinctrl: aspeed-g4: Capture SuperIO pinmux dependency Andrew Jeffery
2016-10-20 11:53 ` Linus Walleij
2016-10-21 0:33 ` Andrew Jeffery
2016-10-23 22:09 ` Linus Walleij
2016-10-24 0:30 ` Andrew Jeffery
2016-09-27 14:50 ` [PATCH 7/8] pinctrl: aspeed-g4: Add mux configuration for all pins Andrew Jeffery
2016-09-29 0:54 ` Joel Stanley
2016-10-03 19:08 ` Rob Herring
2016-10-04 1:02 ` Andrew Jeffery
2016-09-27 14:50 ` [PATCH 8/8] pinctrl: aspeed-g5: " Andrew Jeffery
2016-09-29 0:54 ` Joel Stanley
2016-10-10 0:53 ` Rob Herring
2016-10-10 7:59 ` [PATCH 0/8] pinctrl: aspeed: Fixes for core and g5, implement remaining pins Linus Walleij
2016-10-10 23:27 ` Andrew Jeffery [this message]
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