From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932802AbcJLKOi (ORCPT ); Wed, 12 Oct 2016 06:14:38 -0400 Received: from mga02.intel.com ([134.134.136.20]:62022 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932713AbcJLKNk (ORCPT ); Wed, 12 Oct 2016 06:13:40 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,333,1473145200"; d="scan'208";a="1052743060" From: Grzegorz Andrejczuk To: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org Cc: bp@suse.de, dave.hansen@linux.intel.com, linux-kernel@vger.kernel.org, lukasz.daniluk@intel.com, james.h.cownie@intel.com, Grzegorz Andrejczuk Subject: [PATCH v1 1/4] Add R3MWAIT register and bit to msr-info.h Date: Wed, 12 Oct 2016 12:13:07 +0200 Message-Id: <1476267190-2303-2-git-send-email-grzegorz.andrejczuk@intel.com> X-Mailer: git-send-email 2.5.1 In-Reply-To: <1476267190-2303-1-git-send-email-grzegorz.andrejczuk@intel.com> References: <1476267190-2303-1-git-send-email-grzegorz.andrejczuk@intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Intel Xeon Phi x200 (codenamed Knights Landing) has MSR MISC_THD_FEATURE_ENABLE 0x140. Setting its 2nd bit make MONITOR and MWAIT instructions do not cause invalid-opcode exception. This commit adds this register prefixed by PHI and bit to msr-info.h Reference: https://software.intel.com/en-us/blogs/2016/10/06/intel-xeon-phi-product-family-x200-knl-user-mode-ring-3-monitor-and-mwait Change-Id: If3b14c78f4e66d734e5a00921023a8c7cafc0cf3 Signed-off-by: Grzegorz Andrejczuk --- arch/x86/include/asm/msr-index.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 56f4c66..3eb1713 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -540,6 +540,11 @@ #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) +/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */ +#define MSR_PHI_MISC_THD_FEATURE_ENABLE 0x00000140 +#define MSR_PHI_MISC_THD_FEATURE_ENABLE_R3MWAIT_BIT 1 +#define MSR_PHI_MISC_THD_FEATURE_ENABLE_R3MWAIT (1ULL << MSR_PHI_MISC_THD_FEATURE_ENABLE_R3MWAIT_BIT) + #define MSR_IA32_TSC_DEADLINE 0x000006E0 /* P4/Xeon+ specific */ -- 2.5.1