From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754671AbcJLMSR (ORCPT ); Wed, 12 Oct 2016 08:18:17 -0400 Received: from mga11.intel.com ([192.55.52.93]:32231 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752483AbcJLMSJ (ORCPT ); Wed, 12 Oct 2016 08:18:09 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,482,1473145200"; d="scan'208";a="19261811" From: Grzegorz Andrejczuk To: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org Cc: bp@suse.de, dave.hansen@linux.intel.com, linux-kernel@vger.kernel.org, lukasz.daniluk@intel.com, james.h.cownie@intel.com, Grzegorz Andrejczuk Subject: [PATCH v2 2/4] Add enabling of the R3 MWAIT during boot for KNL Date: Wed, 12 Oct 2016 14:16:23 +0200 Message-Id: <1476274585-21679-3-git-send-email-grzegorz.andrejczuk@intel.com> X-Mailer: git-send-email 2.5.1 In-Reply-To: <1476274585-21679-1-git-send-email-grzegorz.andrejczuk@intel.com> References: <1476274585-21679-1-git-send-email-grzegorz.andrejczuk@intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org If processor is Intel Xeon Phi we enable user-level mwait feature. Enabling this feature suppreses invalid-opcode error, when MONITOR/MWAIT is called from ring 3. Change-Id: I1c7defb99296b022790a068a6c725b3e860cd68c Signed-off-by: Grzegorz Andrejczuk --- arch/x86/kernel/cpu/intel.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index fcd484d..ac6df08 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -61,6 +61,14 @@ void check_mpx_erratum(struct cpuinfo_x86 *c) } } +static int phir3mwait = 1; +static int __init phir3mwait_disable(char *value) +{ + phir3mwait = 0; + return 1; +} +__setup("intel-phir3mwait=disable", phir3mwait_disable); + static void early_init_intel(struct cpuinfo_x86 *c) { u64 misc_enable; @@ -211,6 +219,25 @@ static void early_init_intel(struct cpuinfo_x86 *c) } check_mpx_erratum(c); + + /* + * Setting ring 3 MONITOR/MWAIT for all threads + * when CPU is Xeon Phi Family x200 + * This can be disabled with phir3mwait=disable cmdline switch. + * We preserve the reserved values and set only 2nd bit. + * Ref: + * https://software.intel.com/en-us/blogs/2016/10/06/intel-xeon-phi-product-family-x200-knl-user-mode-ring-3-monitor-and-mwait + */ + if (c->x86 == 6 && + c->x86_model == INTEL_FAM6_XEON_PHI_KNL && + phir3mwait) { + u64 prev; + + rdmsrl(MSR_PHI_MISC_THD_FEATURE, prev); + if ((prev & MSR_PHI_MISC_THD_FEATURE_R3MWAIT) == 0) + wrmsrl(MSR_PHI_MISC_THD_FEATURE, + prev | MSR_PHI_MISC_THD_FEATURE_R3MWAIT); + } } #ifdef CONFIG_X86_32 -- 2.5.1