From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754837AbcJLMTw (ORCPT ); Wed, 12 Oct 2016 08:19:52 -0400 Received: from mga11.intel.com ([192.55.52.93]:32231 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753347AbcJLMSJ (ORCPT ); Wed, 12 Oct 2016 08:18:09 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,482,1473145200"; d="scan'208";a="19261828" From: Grzegorz Andrejczuk To: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org Cc: bp@suse.de, dave.hansen@linux.intel.com, linux-kernel@vger.kernel.org, lukasz.daniluk@intel.com, james.h.cownie@intel.com, Grzegorz Andrejczuk Subject: [PATCH v2 4/4] Add R3MWAIT to CPU features Date: Wed, 12 Oct 2016 14:16:25 +0200 Message-Id: <1476274585-21679-5-git-send-email-grzegorz.andrejczuk@intel.com> X-Mailer: git-send-email 2.5.1 In-Reply-To: <1476274585-21679-1-git-send-email-grzegorz.andrejczuk@intel.com> References: <1476274585-21679-1-git-send-email-grzegorz.andrejczuk@intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add cpu feature for ring 3 monitor/mwait. Change-Id: Iba4d20639efd8d3637d37db9294cbc43a98f009a Signed-off-by: Grzegorz Andrejczuk --- arch/x86/include/asm/cpufeatures.h | 2 ++ arch/x86/kernel/cpu/common.c | 3 +++ arch/x86/kernel/cpu/scattered.c | 5 +++++ 3 files changed, 10 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 92a8308..9caf9c4 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -71,6 +71,8 @@ #define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ #define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */ #define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */ +/* non architectural Intel-defined CPU features not present in CPUID */ +#define X86_FEATURE_PHIR3MWAIT (2*32+ 4) /* Other features, Linux-defined mapping, word 3 */ /* This range is used for feature bits which conflict or are synthesized */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 93ffaa5..15fe27f 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1108,6 +1108,9 @@ static void identify_cpu(struct cpuinfo_x86 *c) #endif /* The boot/hotplug time assigment got cleared, restore it */ c->logical_proc_id = topology_phys_to_logical_pkg(c->phys_proc_id); + + if (cpu_has(c, X86_FEATURE_PHIR3MWAIT)) + elf_hwcap2 |= HWCAP2_PHIR3MWAIT; } /* diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index 8cb57df..e4ff3d0 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -29,6 +29,7 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c) u32 max_level; u32 regs[4]; const struct cpuid_bit *cb; + u64 misc_thd_enable; static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_INTEL_PT, CR_EBX,25, 0x00000007, 0 }, @@ -54,4 +55,8 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c) if (regs[cb->reg] & (1 << cb->bit)) set_cpu_cap(c, cb->feature); } + + rdmsrl(MSR_PHI_MISC_THD_FEATURE, misc_thd_enable); + if ((misc_thd_enable & MSR_PHI_MISC_THD_FEATURE_R3MWAIT) != 0) + set_cpu_cap(c, X86_FEATURE_PHIR3MWAIT); } -- 2.5.1