From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758962AbcJYNFb (ORCPT ); Tue, 25 Oct 2016 09:05:31 -0400 Received: from mail-by2nam01on0085.outbound.protection.outlook.com ([104.47.34.85]:7596 "EHLO NAM01-BY2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753785AbcJYNF2 (ORCPT ); Tue, 25 Oct 2016 09:05:28 -0400 X-Greylist: delayed 1041 seconds by postgrey-1.27 at vger.kernel.org; Tue, 25 Oct 2016 09:05:28 EDT Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed) header.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com;nxp.com; dkim=none (message not signed) header.d=none; From: Minghuan Lian To: , , CC: Shawn Guo , Marc Zyngier , Rob Herring , Mingkai Hu , Stuart Yoder , Yang-Leo Li , Scott Wood , Minghuan Lian Subject: [PATCH 3/6] arm64: dts: ls1043a: update MSI and PCIe node Date: Tue, 25 Oct 2016 20:35:42 +0800 Message-ID: <1477398945-22774-3-git-send-email-Minghuan.Lian@nxp.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1477398945-22774-1-git-send-email-Minghuan.Lian@nxp.com> References: <1477398945-22774-1-git-send-email-Minghuan.Lian@nxp.com> X-EOPAttributedMessage: 0 X-Matching-Connectors: 131218724261872060;(91ab9b29-cfa4-454e-5278-08d120cd25b8);() X-Forefront-Antispam-Report: CIP:192.88.168.50;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(7916002)(2980300002)(1109001)(1110001)(339900001)(189002)(199003)(106466001)(50466002)(7846002)(19580405001)(229853001)(19580395003)(4326007)(2201001)(105606002)(77096005)(356003)(2950100002)(76176999)(86362001)(50986999)(87936001)(47776003)(8666005)(81166006)(189998001)(8676002)(2906002)(85426001)(5003940100001)(81156014)(68736007)(586003)(97736004)(305945005)(11100500001)(5001770100001)(5660300001)(7416002)(48376002)(8936002)(36756003)(626004)(104016004)(50226002)(92566002)(7059030)(2101003);DIR:OUT;SFP:1101;SCL:1;SRVR:CY1PR0301MB1625;H:tx30smr01.am.freescale.net;FPR:;SPF:Fail;PTR:InfoDomainNonexistent;MX:1;A:1;LANG:en; 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Change compatible to "fsl,ls-scfg-msi" 2. Move three MSI dts node into the parent node "msi-controller". So a PCIe device can request the MSI from the three MSI controllers. 3. The rev1.1 of LS1043a moves PCIe INTB/C/D interrupts to MSI controller. Signed-off-by: Minghuan Lian --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 64 +++++++++++++------------- 1 file changed, 33 insertions(+), 31 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 41e5dc1..5295bb9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -587,25 +587,36 @@ dma-coherent; }; - msi1: msi-controller1@1571000 { - compatible = "fsl,1s1043a-msi"; - reg = <0x0 0x1571000 0x0 0x8>; + msi: msi-controller { + compatible = "fsl,ls-scfg-msi"; + #address-cells = <2>; + #size-cells = <2>; + ranges; msi-controller; - interrupts = <0 116 0x4>; - }; - msi2: msi-controller2@1572000 { - compatible = "fsl,1s1043a-msi"; - reg = <0x0 0x1572000 0x0 0x8>; - msi-controller; - interrupts = <0 126 0x4>; - }; + msi0@1571000 { + reg = <0x0 0x1571000 0x0 0x1000>; + interrupts = <0 116 0x4>, + <0 111 0x4>, + <0 112 0x4>, + <0 113 0x4>; + }; - msi3: msi-controller3@1573000 { - compatible = "fsl,1s1043a-msi"; - reg = <0x0 0x1573000 0x0 0x8>; - msi-controller; - interrupts = <0 160 0x4>; + msi1@1572000 { + reg = <0x0 0x1572000 0x0 0x1000>; + interrupts = <0 126 0x4>, + <0 121 0x4>, + <0 122 0x4>, + <0 123 0x4>; + }; + + msi2@1573000 { + reg = <0x0 0x1573000 0x0 0x1000>; + interrupts = <0 160 0x4>, + <0 155 0x4>, + <0 156 0x4>, + <0 157 0x4>; + }; }; pcie@3400000 { @@ -624,13 +635,10 @@ bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi1>; + msi-parent = <&msi>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, - <0000 0 0 2 &gic 0 111 0x4>, - <0000 0 0 3 &gic 0 112 0x4>, - <0000 0 0 4 &gic 0 113 0x4>; + interrupt-map = <0000 0 0 1 &gic 0 110 0x4>; }; pcie@3500000 { @@ -649,13 +657,10 @@ bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi2>; + msi-parent = <&msi>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, - <0000 0 0 2 &gic 0 121 0x4>, - <0000 0 0 3 &gic 0 122 0x4>, - <0000 0 0 4 &gic 0 123 0x4>; + interrupt-map = <0000 0 0 1 &gic 0 120 0x4>; }; pcie@3600000 { @@ -674,13 +679,10 @@ bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi3>; + msi-parent = <&msi>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, - <0000 0 0 2 &gic 0 155 0x4>, - <0000 0 0 3 &gic 0 156 0x4>, - <0000 0 0 4 &gic 0 157 0x4>; + interrupt-map = <0000 0 0 1 &gic 0 154 0x4>; }; }; -- 1.9.1