From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966003AbcJ1R0i (ORCPT ); Fri, 28 Oct 2016 13:26:38 -0400 Received: from mail-sn1nam02on0084.outbound.protection.outlook.com ([104.47.36.84]:45312 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1756452AbcJ1R0h (ORCPT ); Fri, 28 Oct 2016 13:26:37 -0400 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Yazen.Ghannam@amd.com; From: Yazen Ghannam To: CC: , , Yazen Ghannam , Subject: [PATCH v2 1/2] x86/AMD: Fix cpu_llc_id for AMD Fam17h systems Date: Fri, 28 Oct 2016 10:51:57 -0500 Message-ID: <1477669918-56261-1-git-send-email-Yazen.Ghannam@amd.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: BY2PR05CA061.namprd05.prod.outlook.com (10.141.250.51) To DM5PR12MB1388.namprd12.prod.outlook.com (10.168.238.139) X-MS-Office365-Filtering-Correlation-Id: 717ea52a-eeba-45e7-47c1-08d3ff4a6a95 X-Microsoft-Exchange-Diagnostics: 1;DM5PR12MB1388;2:ptcQzba+KviH955Ce0u3pNwWIoCKveLpu6RVfK6pB078V999WQY9ILY9KRRKKJ1BQxAocL0FcjzI47PvmzlbFkQJre7fWFOBE/s2YE9vJ/MpI7bBS2iiAh1sAFLU+7vxitBVxQAuh70hrT/3hvIOa5gBcjwDv3KzMiGfM2SKYJ5T8YNeZhtPcWzyYOyVT8xxcaa77BLsVvhAloaMk1vCdw==;3:0B2aZIiI8X3PpvY/Myj4Llu6t32syMbH5aUdZKXuctChBwrf58IFWxI1vt1F+Eb+0U1b/02wh7ZfVv9AZk2eWS3xO+NeHpIh/9xcXrgza4caZfvD0sK3sE1/FWCgXSZEEYUnWjHyUXKOmacWxdonow== X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:DM5PR12MB1388; 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The socket_id value starts from 0, so subtracting 1 will result in an underflow. This breaks scheduling topology later on since the cpu_llc_id will be incorrect. The apicid decoding is fixed for bits 3 and above, which give the core complex, node and socket IDs. The LLC is at the core complex level so we can find a unique cpu_llc_id by right shifting the apicid by 3. We can fix the underflow bug and simplify the code by replacing the current cpu_llc_id derivation with a right shift. Signed-off-by: Yazen Ghannam Cc: # v4.4.. Fixes: 3849e91f571d ("x86/AMD: Fix last level cache topology for AMD Fam17h systems") --- arch/x86/kernel/cpu/amd.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 7b76eb6..c3fc337 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -347,7 +347,6 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c) #ifdef CONFIG_SMP unsigned bits; int cpu = smp_processor_id(); - unsigned int socket_id, core_complex_id; bits = c->x86_coreid_bits; /* Low order bits define the core id (index of core in socket) */ @@ -365,10 +364,7 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c) if (c->x86 != 0x17 || !cpuid_edx(0x80000006)) return; - socket_id = (c->apicid >> bits) - 1; - core_complex_id = (c->apicid & ((1 << bits) - 1)) >> 3; - - per_cpu(cpu_llc_id, cpu) = (socket_id << 3) | core_complex_id; + per_cpu(cpu_llc_id, cpu) = c->apicid >> 3; #endif } -- 1.9.1