From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753405AbcKARXW (ORCPT ); Tue, 1 Nov 2016 13:23:22 -0400 Received: from mail-by2nam01on0050.outbound.protection.outlook.com ([104.47.34.50]:49280 "EHLO NAM01-BY2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750832AbcKARXT (ORCPT ); Tue, 1 Nov 2016 13:23:19 -0400 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Yazen.Ghannam@amd.com; From: Yazen Ghannam To: CC: , , Yazen Ghannam , Subject: [PATCH v3 1/2] x86/AMD: Fix cpu_llc_id for AMD Fam17h systems Date: Tue, 1 Nov 2016 11:51:02 -0500 Message-ID: <1478019063-2632-1-git-send-email-Yazen.Ghannam@amd.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: BY2PR05CA051.namprd05.prod.outlook.com (10.141.250.41) To MWHPR12MB1389.namprd12.prod.outlook.com (10.169.206.12) X-MS-Office365-Filtering-Correlation-Id: ca91cace-0f87-4ee1-a215-08d402774d63 X-Microsoft-Exchange-Diagnostics: 1;MWHPR12MB1389;2:66Ldlu+Dmo6lWmjGuXL+vu9sN8llbdgyiMrNpfQOQdKFfvRYpCZLC9a/BHVNvsEUi/GY8g2I62X6gYZ+EOBLlIHLaaMLE6n2NNK7Hu5U7GG6e9w52OfpEhZ2GLeh6lSo1kTyklwJ0MoVsWOqYxVND2hkK0DDU4y76E60tPnveSs7d7ckVVTh8VAzin3zlrW3/FhjWc5Vw1ivA1vDmnAwtg==;3:7ePrdptEDVRocTgktV5sYrjzafhyZ1v8iIrKOSSUSalh9yZv2ypRv3NpYonh5QHfWu69ADpl8upvbxeHiRncVVvBKfJSHevPbH5KEslUk/OcAXDA2ha+TWltzF6fA1hn/ixPXCMuywMOOu4eF/fAUQ== X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:MWHPR12MB1389; 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The socket_id value starts from 0, so subtracting 1 will result in an underflow. This breaks scheduling topology later on since the cpu_llc_id will be incorrect. The APICID decoding is fixed, in register, for bits 3 and above, which give the core complex, node and socket IDs. The LLC is at the core complex level so we can find a unique cpu_llc_id by right shifting the APICID by 3 because then the least significant bit will be the Core Complex ID. We can fix the underflow bug and simplify the code by replacing the current cpu_llc_id derivation with a right shift. Signed-off-by: Yazen Ghannam Cc: # v4.4.. Fixes: 3849e91f571d ("x86/AMD: Fix last level cache topology for AMD Fam17h systems") --- Link: http://lkml.kernel.org/r/1477669918-56261-1-git-send-email-Yazen.Ghannam@amd.com v2->v3: * Fixup commit message based on comments. arch/x86/kernel/cpu/amd.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index b81fe2d..1e81a37 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -347,7 +347,6 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c) #ifdef CONFIG_SMP unsigned bits; int cpu = smp_processor_id(); - unsigned int socket_id, core_complex_id; bits = c->x86_coreid_bits; /* Low order bits define the core id (index of core in socket) */ @@ -365,10 +364,7 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c) if (c->x86 != 0x17 || !cpuid_edx(0x80000006)) return; - socket_id = (c->apicid >> bits) - 1; - core_complex_id = (c->apicid & ((1 << bits) - 1)) >> 3; - - per_cpu(cpu_llc_id, cpu) = (socket_id << 3) | core_complex_id; + per_cpu(cpu_llc_id, cpu) = c->apicid >> 3; #endif } -- 1.9.1