From: Bin Gao <bin.gao@intel.com>
To: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, H Peter Anvin <hpa@zytor.com>,
x86@kernel.org
Cc: Peter Zijlstra <peterz@infradead.org>,
linux-kernel@vger.kernel.org, Bin Gao <bin.gao@intel.com>
Subject: [PATCH 0/2] x86/tsc: split X86_FEATURE_TSC_RELIABLE into two
Date: Tue, 1 Nov 2016 10:14:40 -0700 [thread overview]
Message-ID: <1478020482-231459-1-git-send-email-bin.gao@intel.com> (raw)
This patch series split X86_FEATURE_TSC_RELIABLE into two separate
flags: X86_FEATURE_TSC_RELIABLE and X86_FEATURE_TSC_KNOWN_FREQ.
This change allows us to redefine TSC features at fine granularity.
This is driven by certain Intel processors/SoCs with frequency-known
TSC so the whole calibration stuff should be skipped.
Bin Gao (2):
x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag
x86: use KNOWN_FREQ and RELIABLE TSC flags on certain processors/SoCs
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kernel/tsc.c | 15 ++++++++++++---
arch/x86/kernel/tsc_msr.c | 4 ++++
arch/x86/platform/intel-mid/mfld.c | 5 +++--
arch/x86/platform/intel-mid/mrfld.c | 4 ++--
5 files changed, 22 insertions(+), 7 deletions(-)
--
1.9.1
next reply other threads:[~2016-11-01 17:08 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-01 17:14 Bin Gao [this message]
2016-11-01 17:14 ` [PATCH 1/2] x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag Bin Gao
2016-11-09 21:09 ` Thomas Gleixner
[not found] ` <4460FA1017EA3844B646E90DA4E984057E2ECB7C@ORSMSX112.amr.corp.intel.com>
2016-11-10 22:51 ` Bin Gao
2016-11-01 17:14 ` [PATCH 2/2] x86: use KNOWN_FREQ and RELIABLE TSC flags on certain processors/SoCs Bin Gao
2016-11-09 21:25 ` Thomas Gleixner
[not found] ` <4460FA1017EA3844B646E90DA4E984057E2ECB85@ORSMSX112.amr.corp.intel.com>
2016-11-10 23:20 ` Bin Gao
2016-11-10 23:26 ` Thomas Gleixner
2016-11-11 0:06 ` Bin Gao
2016-11-11 0:01 ` Thomas Gleixner
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