From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755913AbcKBOj6 (ORCPT ); Wed, 2 Nov 2016 10:39:58 -0400 Received: from out2-smtp.messagingengine.com ([66.111.4.26]:46377 "EHLO out2-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755833AbcKBOji (ORCPT ); Wed, 2 Nov 2016 10:39:38 -0400 X-ME-Sender: X-Sasl-enc: HD91gRBbxNd0c8rbZhnri5+xtmOkm/UOSWtPAu6255Oe 1478097576 From: Andrew Jeffery To: Lee Jones , Linus Walleij Cc: Joel Stanley , Mark Rutland , Rob Herring , linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Andrew Jeffery Subject: [PATCH v2 3/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LPCHC) Date: Thu, 3 Nov 2016 01:07:58 +1030 Message-Id: <1478097481-14895-4-git-send-email-andrew@aj.id.au> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1478097481-14895-1-git-send-email-andrew@aj.id.au> References: <1478097481-14895-1-git-send-email-andrew@aj.id.au> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Aspeed LPC Host Controller is presented as a syscon device to arbitrate access by LPC and pinmux drivers. LPC pinmux configuration on fifth generation SoCs depends on bits in both the System Control Unit and the LPC Host Controller. Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt new file mode 100644 index 000000000000..792651488c3d --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt @@ -0,0 +1,17 @@ +* Device tree bindings for the Aspeed LPC Host Controller (LPCHC) + +The LPCHC registers configure LPC behaviour between the BMC and the host +system. The LPCHC also participates in pinmux requests on g5 SoCs and is +therefore considered a syscon device. + +Required properties: +- compatible: "aspeed,ast2500-lpchc", "syscon" +- reg: contains offset/length value of the LPCHC memory + region. + +Example: + +lpchc: lpchc@1e7890a0 { + compatible = "aspeed,ast2500-lpchc", "syscon"; + reg = <0x1e7890a0 0xc4>; +}; -- 2.7.4