From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965515AbcKXNmI (ORCPT ); Thu, 24 Nov 2016 08:42:08 -0500 Received: from foss.arm.com ([217.140.101.70]:51456 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S940997AbcKXNlG (ORCPT ); Thu, 24 Nov 2016 08:41:06 -0500 From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com, dave.martin@arm.com, aph@redhat.com, will.deacon@arm.com, ryan.arnold@linaro.org, sid@reserved-bit.com, adhemerval.zanella@linaro.org, mark.rutland@arm.com, marc.zyngier@arm.com, Suzuki K Poulose Subject: [PATCH 5/9] arm64: cpufeature: Define helpers for sys_reg id Date: Thu, 24 Nov 2016 13:40:05 +0000 Message-Id: <1479994809-9081-6-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1479994809-9081-1-git-send-email-suzuki.poulose@arm.com> References: <1479994809-9081-1-git-send-email-suzuki.poulose@arm.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Define helper macros to extract op0, op1, CRn, CRm & op2 for a given sys_reg id. Cc: Catalin Marinas Cc: Mark Rutland Cc: Will Deacon Signed-off-by: Suzuki K Poulose --- arch/arm64/include/asm/sysreg.h | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 6c80b36..488b939 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -34,8 +34,27 @@ * [11-8] : CRm * [7-5] : Op2 */ +#define Op0_shift 19 +#define Op0_mask 0x3 +#define Op1_shift 16 +#define Op1_mask 0x7 +#define CRn_shift 12 +#define CRn_mask 0xf +#define CRm_shift 8 +#define CRm_mask 0xf +#define Op2_shift 5 +#define Op2_mask 0x7 + #define sys_reg(op0, op1, crn, crm, op2) \ - ((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5)) + ((((op0) & Op0_mask) << Op0_shift) | \ + ((op1) << Op1_shift) | ((crn) << CRn_shift) | \ + ((crm) << CRm_shift) | ((op2) << Op2_shift)) + +#define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask) +#define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask) +#define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask) +#define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask) +#define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask) #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) -- 2.7.4