From: Peter Rosin <peda@axentia.se>
To: <linux-kernel@vger.kernel.org>
Cc: Peter Rosin <peda@axentia.se>,
Linus Walleij <linus.walleij@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
"Andrey Smirnov" <andrew.smirnov@gmail.com>,
Neil Armstrong <narmstrong@baylibre.com>,
<linux-gpio@vger.kernel.org>, <devicetree@vger.kernel.org>
Subject: [PATCH 2/3] pinctrl: sx150x: sort chips by part number
Date: Thu, 24 Nov 2016 21:45:19 +0100 [thread overview]
Message-ID: <1480020320-28354-3-git-send-email-peda@axentia.se> (raw)
In-Reply-To: <1480020320-28354-1-git-send-email-peda@axentia.se>
Signed-off-by: Peter Rosin <peda@axentia.se>
---
.../devicetree/bindings/pinctrl/pinctrl-sx150x.txt | 6 +-
drivers/pinctrl/pinctrl-sx150x.c | 142 ++++++++++-----------
2 files changed, 74 insertions(+), 74 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt
index 25b4ec80c759..83f8d5c449ba 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt
@@ -6,11 +6,11 @@ pin controller, GPIO, and interrupt bindings.
Required properties:
- compatible: should be one of :
+ "semtech,sx1502q",
+ "semtech,sx1503q",
"semtech,sx1506q",
"semtech,sx1508q",
- "semtech,sx1509q",
- "semtech,sx1502q",
- "semtech,sx1503q".
+ "semtech,sx1509q".
- reg: The I2C slave address for this device.
diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c
index a19c814843aa..97df9302e84b 100644
--- a/drivers/pinctrl/pinctrl-sx150x.c
+++ b/drivers/pinctrl/pinctrl-sx150x.c
@@ -148,71 +148,6 @@ static const struct pinctrl_pin_desc sx150x_16_pins[] = {
PINCTRL_PIN(16, "oscio"),
};
-static const struct sx150x_device_data sx1508q_device_data = {
- .model = SX150X_789,
- .reg_pullup = 0x03,
- .reg_pulldn = 0x04,
- .reg_dir = 0x07,
- .reg_data = 0x08,
- .reg_irq_mask = 0x09,
- .reg_irq_src = 0x0c,
- .reg_sense = 0x0a,
- .pri.x789 = {
- .reg_drain = 0x05,
- .reg_polarity = 0x06,
- .reg_clock = 0x0f,
- .reg_misc = 0x10,
- .reg_reset = 0x7d,
- },
- .ngpios = 8,
- .pins = sx150x_8_pins,
- .npins = ARRAY_SIZE(sx150x_8_pins),
-};
-
-static const struct sx150x_device_data sx1509q_device_data = {
- .model = SX150X_789,
- .reg_pullup = 0x06,
- .reg_pulldn = 0x08,
- .reg_dir = 0x0e,
- .reg_data = 0x10,
- .reg_irq_mask = 0x12,
- .reg_irq_src = 0x18,
- .reg_sense = 0x14,
- .pri.x789 = {
- .reg_drain = 0x0a,
- .reg_polarity = 0x0c,
- .reg_clock = 0x1e,
- .reg_misc = 0x1f,
- .reg_reset = 0x7d,
- },
- .ngpios = 16,
- .pins = sx150x_16_pins,
- .npins = ARRAY_SIZE(sx150x_16_pins),
-};
-
-static const struct sx150x_device_data sx1506q_device_data = {
- .model = SX150X_456,
- .reg_pullup = 0x04,
- .reg_pulldn = 0x06,
- .reg_dir = 0x02,
- .reg_data = 0x00,
- .reg_irq_mask = 0x08,
- .reg_irq_src = 0x0e,
- .reg_sense = 0x0a,
- .pri.x456 = {
- .reg_pld_mode = 0x20,
- .reg_pld_table0 = 0x22,
- .reg_pld_table1 = 0x24,
- .reg_pld_table2 = 0x26,
- .reg_pld_table3 = 0x28,
- .reg_pld_table4 = 0x2a,
- .reg_advance = 0xad,
- },
- .ngpios = 16,
- .pins = sx150x_16_pins,
- .npins = 16, /* oscio not available */
-};
-
static const struct sx150x_device_data sx1502q_device_data = {
.model = SX150X_123,
.reg_pullup = 0x02,
@@ -259,6 +194,71 @@ static const struct sx150x_device_data sx1503q_device_data = {
.npins = 16, /* oscio not available */
};
+static const struct sx150x_device_data sx1506q_device_data = {
+ .model = SX150X_456,
+ .reg_pullup = 0x04,
+ .reg_pulldn = 0x06,
+ .reg_dir = 0x02,
+ .reg_data = 0x00,
+ .reg_irq_mask = 0x08,
+ .reg_irq_src = 0x0e,
+ .reg_sense = 0x0a,
+ .pri.x456 = {
+ .reg_pld_mode = 0x20,
+ .reg_pld_table0 = 0x22,
+ .reg_pld_table1 = 0x24,
+ .reg_pld_table2 = 0x26,
+ .reg_pld_table3 = 0x28,
+ .reg_pld_table4 = 0x2a,
+ .reg_advance = 0xad,
+ },
+ .ngpios = 16,
+ .pins = sx150x_16_pins,
+ .npins = 16, /* oscio not available */
+};
+
+static const struct sx150x_device_data sx1508q_device_data = {
+ .model = SX150X_789,
+ .reg_pullup = 0x03,
+ .reg_pulldn = 0x04,
+ .reg_dir = 0x07,
+ .reg_data = 0x08,
+ .reg_irq_mask = 0x09,
+ .reg_irq_src = 0x0c,
+ .reg_sense = 0x0a,
+ .pri.x789 = {
+ .reg_drain = 0x05,
+ .reg_polarity = 0x06,
+ .reg_clock = 0x0f,
+ .reg_misc = 0x10,
+ .reg_reset = 0x7d,
+ },
+ .ngpios = 8,
+ .pins = sx150x_8_pins,
+ .npins = ARRAY_SIZE(sx150x_8_pins),
+};
+
+static const struct sx150x_device_data sx1509q_device_data = {
+ .model = SX150X_789,
+ .reg_pullup = 0x06,
+ .reg_pulldn = 0x08,
+ .reg_dir = 0x0e,
+ .reg_data = 0x10,
+ .reg_irq_mask = 0x12,
+ .reg_irq_src = 0x18,
+ .reg_sense = 0x14,
+ .pri.x789 = {
+ .reg_drain = 0x0a,
+ .reg_polarity = 0x0c,
+ .reg_clock = 0x1e,
+ .reg_misc = 0x1f,
+ .reg_reset = 0x7d,
+ },
+ .ngpios = 16,
+ .pins = sx150x_16_pins,
+ .npins = ARRAY_SIZE(sx150x_16_pins),
+};
+
static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
return 0;
@@ -758,20 +758,20 @@ static const struct pinconf_ops sx150x_pinconf_ops = {
};
static const struct i2c_device_id sx150x_id[] = {
- {"sx1508q", (kernel_ulong_t) &sx1508q_device_data },
- {"sx1509q", (kernel_ulong_t) &sx1509q_device_data },
- {"sx1506q", (kernel_ulong_t) &sx1506q_device_data },
{"sx1502q", (kernel_ulong_t) &sx1502q_device_data },
{"sx1503q", (kernel_ulong_t) &sx1503q_device_data },
+ {"sx1506q", (kernel_ulong_t) &sx1506q_device_data },
+ {"sx1508q", (kernel_ulong_t) &sx1508q_device_data },
+ {"sx1509q", (kernel_ulong_t) &sx1509q_device_data },
{}
};
static const struct of_device_id sx150x_of_match[] = {
- { .compatible = "semtech,sx1508q", .data = &sx1508q_device_data },
- { .compatible = "semtech,sx1509q", .data = &sx1509q_device_data },
- { .compatible = "semtech,sx1506q", .data = &sx1506q_device_data },
{ .compatible = "semtech,sx1502q", .data = &sx1502q_device_data },
{ .compatible = "semtech,sx1503q", .data = &sx1503q_device_data },
+ { .compatible = "semtech,sx1506q", .data = &sx1506q_device_data },
+ { .compatible = "semtech,sx1508q", .data = &sx1508q_device_data },
+ { .compatible = "semtech,sx1509q", .data = &sx1509q_device_data },
{},
};
--
2.1.4
next prev parent reply other threads:[~2016-11-24 23:22 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-24 20:45 [PATCH 0/3] sx150x update - bugfix, cleanup, last 4 chips Peter Rosin
2016-11-24 20:45 ` [PATCH 1/3] pinctrl: sx150x: use correct registers for reg_sense (sx1502 and sx1508) Peter Rosin
2016-11-25 13:40 ` Linus Walleij
2016-12-02 8:56 ` Peter Rosin
2016-11-24 20:45 ` Peter Rosin [this message]
2016-11-25 13:41 ` [PATCH 2/3] pinctrl: sx150x: sort chips by part number Linus Walleij
2016-11-24 20:45 ` [PATCH 3/3] pinctrl: sx150x: add support for sx1501, sx1504, sx1505 and sx1507 Peter Rosin
2016-11-24 21:02 ` Peter Rosin
2016-11-25 13:45 ` Linus Walleij
2016-11-25 15:24 ` Neil Armstrong
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