From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933895AbcK3PPb (ORCPT ); Wed, 30 Nov 2016 10:15:31 -0500 Received: from foss.arm.com ([217.140.101.70]:49424 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932270AbcK3PPX (ORCPT ); Wed, 30 Nov 2016 10:15:23 -0500 From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com, dave.martin@arm.com, aph@redhat.com, will.deacon@arm.com, ryan.arnold@linaro.org, sid@reserved-bit.com, adhemerval.zanella@linaro.org, mark.rutland@arm.com, marc.zyngier@arm.com, Suzuki K Poulose Subject: [PATCH v2 0/9] arm64: Expose CPUID registers via emulation Date: Wed, 30 Nov 2016 15:14:51 +0000 Message-Id: <1480518901-18544-1-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This series adds a new ABI to expose the CPU feature registers to the user space via emulation of MRS instruction. The system exposes only a limited set of feature values (See the documentation patch) from the cpufeature infrastructure. The feature bits that are not exposed are set to the 'safe value' which implies 'not supported'. Apart from the selected feature registers, we expose MIDR_EL1 (Main ID Register). The user should be aware that, reading MIDR_EL1 can be tricky on a heterogeneous system (just like getcpu()). We export the value of the current CPU where 'MRS' is executed. Changes since V1: - Drop mask for Op0 in sys_reg() - Fix documentation - Change safe value of MPIDR to drop MT support - Do not emulate AArch32 ID registers Mark Rutland (2): arm64: cpufeature: treat unknown fields as RES0 arm64: cpufeature: remove explicit RAZ fields Suzuki K Poulose (7): arm64: cpufeature: Cleanup feature bit tables arm64: cpufeature: Document the rules of safe value for features arm64: cpufeature: Define helpers for sys_reg id arm64: Add helper to decode register from instruction arm64: cpufeature: Track user visible fields arm64: cpufeature: Expose CPUID registers by emulation arm64: Documentation - Expose CPU feature registers Documentation/arm64/cpu-feature-registers.txt | 196 +++++++++++++++ arch/arm64/include/asm/cpufeature.h | 27 +- arch/arm64/include/asm/insn.h | 2 + arch/arm64/include/asm/sysreg.h | 25 +- arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 340 +++++++++++++++++--------- arch/arm64/kernel/cpuinfo.c | 1 + arch/arm64/kernel/insn.c | 29 +++ arch/arm64/kernel/traps.c | 2 +- 9 files changed, 502 insertions(+), 121 deletions(-) create mode 100644 Documentation/arm64/cpu-feature-registers.txt -- 2.7.4