From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S968986AbdADSrl (ORCPT ); Wed, 4 Jan 2017 13:47:41 -0500 Received: from foss.arm.com ([217.140.101.70]:56398 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966444AbdADSpr (ORCPT ); Wed, 4 Jan 2017 13:45:47 -0500 From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will.deacon@arm.com, mark.rutland@arm.com, dave.martin@arm.com, aph@redhat.com, ryan.arnold@linaro.org, adhemerval.zanella@linaro.org, sid@reserved-bit.com, Suzuki K Poulose Subject: [PATCH v3 3/9] arm64: cpufeature: Cleanup feature bit tables Date: Wed, 4 Jan 2017 17:49:01 +0000 Message-Id: <1483552147-9605-4-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1483552147-9605-1-git-send-email-suzuki.poulose@arm.com> References: <1483552147-9605-1-git-send-email-suzuki.poulose@arm.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch does the following clean ups : 1) All undescribed fields of a register are now treated as "strict" with a safe value of 0. Hence we could leave an empty table for describing registers which are RAZ. 2) ID_AA64DFR1_EL1 is RAZ and should use the table for RAZ register. 3) ftr_generic32 is used to represent a register with a 32bit feature value. Rename this to ftr_singl32 to make it more obvious. Since we don't have a 64bit singe feature register, kill ftr_generic. Based on a patch by Mark Rutland. Cc: Catalin Marinas Cc: Will Deacon Reviewed-by: Mark Rutland Signed-off-by: Suzuki K Poulose --- arch/arm64/kernel/cpufeature.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 72bda9d..fb519e1 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -247,18 +247,13 @@ static const struct arm64_ftr_bits ftr_generic_32bits[] = { ARM64_FTR_END, }; -static const struct arm64_ftr_bits ftr_generic[] = { - ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0), - ARM64_FTR_END, -}; - -static const struct arm64_ftr_bits ftr_generic32[] = { +/* Table for a single 32bit feature value */ +static const struct arm64_ftr_bits ftr_single32[] = { ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0), ARM64_FTR_END, }; -static const struct arm64_ftr_bits ftr_aa64raz[] = { - ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0), +static const struct arm64_ftr_bits ftr_raz[] = { ARM64_FTR_END, }; @@ -299,15 +294,15 @@ static const struct __ftr_reg_entry { /* Op1 = 0, CRn = 0, CRm = 4 */ ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), - ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz), + ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_raz), /* Op1 = 0, CRn = 0, CRm = 5 */ ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), - ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic), + ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), /* Op1 = 0, CRn = 0, CRm = 6 */ ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), - ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz), + ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_raz), /* Op1 = 0, CRn = 0, CRm = 7 */ ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), @@ -319,7 +314,7 @@ static const struct __ftr_reg_entry { ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), /* Op1 = 3, CRn = 14, CRm = 0 */ - ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32), + ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), }; static int search_cmp_ftr_reg(const void *id, const void *regp) -- 2.7.4