From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.smtpout.orange.fr (smtp-66.smtpout.orange.fr [80.12.242.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB0C21E0B86 for ; Mon, 6 Jan 2025 22:00:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.12.242.66 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736200827; cv=none; b=U0xEWw75gEIGOoLIuuaf1loSIlcDRUMneN5RsWT0kAlW8RUm+jAsctRbf+3pwZlKcnt25mL8e+uSaQGwamjkBzcpFOTNeuH9tni6uVqlUbbQ4r6JaVstERFwpUw5rPraMM00F6A4jIeADm9ok3sGyrYSLSB3r3Za5ZsgKIrCWy8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736200827; c=relaxed/simple; bh=rI/y6h0dsuD5a1XaW3ZNBPOLxRFIp2lHLX0sPKhv8UU=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=nTZ0N4uMHiEtsvUCOsMldfygvo/QJKfogMd9O+Ep1p0kxcNYqoFcs2iIiLgdFGrOTcPYIRBeVnQdvVcevpq6PStwxjqTjeboWDD6HfmndraiSIvzX4zdKlK/so0duUi6CtoUZ5RFqEu0hkpNH4RmlMH1cnpKHvMFJQOjIJKON/0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=wanadoo.fr; spf=pass smtp.mailfrom=wanadoo.fr; dkim=pass (2048-bit key) header.d=wanadoo.fr header.i=@wanadoo.fr header.b=Knj/XA/g; arc=none smtp.client-ip=80.12.242.66 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=wanadoo.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=wanadoo.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=wanadoo.fr header.i=@wanadoo.fr header.b="Knj/XA/g" Received: from [192.168.1.37] ([90.11.132.44]) by smtp.orange.fr with ESMTPA id Uv8xtgasrGcOqUv91t2CGv; Mon, 06 Jan 2025 23:00:21 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=wanadoo.fr; s=t20230301; t=1736200821; bh=QnVrWEUtFgMvDpm5kd+ZvPWkuuGKmlEREXeXjJ/9WLQ=; h=Message-ID:Date:MIME-Version:Subject:To:From; b=Knj/XA/gpVUzVe4EkuDhwlNFpl7y04M6/5moZxeMxboXoZUWYOr6qlzRTqtNuWBG3 /MnW8YwGCMviEcnoV2JqsUluyeTkycD2nxfjYZNiruOjvLaYogZZzY8oAl9m4Td24Y pYg4Z/jrut/XM9F6y3h1nqdZjtdy8lAW3t1w2sAQOXYO8ydYIYuV9CEMwd1PVh76v4 dqN9MflSQIWoZLVHXI3jOeiNuM5l8w4ZDt4Z1lfzhl3nfXKopCzzM8JLePvtwthV7G LgXUMF95kAPUbB/M3yziRIliIN0woQ5by3smNzPMLz37eOdsxGpb4RgmhK0oBuSvy/ QfRYsK8viiV7g== X-ME-Helo: [192.168.1.37] X-ME-Auth: bWFyaW9uLmphaWxsZXRAd2FuYWRvby5mcg== X-ME-Date: Mon, 06 Jan 2025 23:00:21 +0100 X-ME-IP: 90.11.132.44 Message-ID: <1483780d-115f-4555-82b3-3e9cffe82dce@wanadoo.fr> Date: Mon, 6 Jan 2025 23:00:14 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] phy: cadence-torrent: Add PCIe multilink configuration for 100 MHz refclk To: Siddharth Vadapalli , vkoul@kernel.org, kishon@kernel.org, sjakhade@cadence.com, rogerq@kernel.org, thomas.richard@bootlin.com, u.kleine-koenig@baylibre.com, eballetb@redhat.com Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, srk@ti.com References: <20250106131925.263240-1-s-vadapalli@ti.com> <20250106131925.263240-2-s-vadapalli@ti.com> Content-Language: en-US, fr-FR From: Christophe JAILLET In-Reply-To: <20250106131925.263240-2-s-vadapalli@ti.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Le 06/01/2025 à 14:19, Siddharth Vadapalli a écrit : > From: Swapnil Jakhade > > Add register sequences to support PCIe multilink configuration for 100MHz > reference clock. Maximum two PCIe links are supported. > > Signed-off-by: Swapnil Jakhade > Signed-off-by: Siddharth Vadapalli > --- > > ***NOTE*** > Since I don't have the hardware required to validate PCIe Multilink + > USB functionality, kindly *do not merge* this series until it gets a > "Tested-by" tag with proper validation of the functionality. > > Regards, > Siddharth. > > drivers/phy/cadence/phy-cadence-torrent.c | 130 +++++++++++++++++++++- > 1 file changed, 129 insertions(+), 1 deletion(-) > > diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c > index a281c0dfae97..b0b5f4bdd7e2 100644 > --- a/drivers/phy/cadence/phy-cadence-torrent.c > +++ b/drivers/phy/cadence/phy-cadence-torrent.c > @@ -197,6 +197,7 @@ > #define RX_SDCAL1_INIT_TMR 0x004CU > #define RX_SDCAL1_ITER_TMR 0x004DU > #define RX_CDRLF_CNFG 0x0080U > +#define RX_CDRLF_CNFG2 0x0081U > #define RX_CDRLF_CNFG3 0x0082U > #define RX_SIGDET_HL_FILT_TMR 0x0090U > #define RX_REE_GCSM1_CTRL 0x0108U > @@ -204,6 +205,7 @@ > #define RX_REE_GCSM1_EQENM_PH2 0x010AU > #define RX_REE_GCSM2_CTRL 0x0110U > #define RX_REE_PERGCSM_CTRL 0x0118U > +#define RX_REE_PEAK_UTHR 0x0142U > #define RX_REE_ATTEN_THR 0x0149U > #define RX_REE_TAP1_CLIP 0x0171U > #define RX_REE_TAP2TON_CLIP 0x0172U > @@ -212,6 +214,7 @@ > #define RX_DIAG_DFE_CTRL 0x01E0U > #define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U > #define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U > +#define RX_DIAG_REE_DAC_CTRL 0x01E4U > #define RX_DIAG_NQST_CTRL 0x01E5U > #define RX_DIAG_SIGDET_TUNE 0x01E8U > #define RX_DIAG_PI_RATE 0x01F4U > @@ -3131,6 +3134,101 @@ static void cdns_torrent_phy_remove(struct platform_device *pdev) > cdns_torrent_clk_cleanup(cdns_phy); > } > > +/* Multi link PCIe configuration */ > +static struct cdns_reg_pairs ml_pcie_link_cmn_regs[] = { > + {0x0002, PHY_PLL_CFG}, > + {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0} > +}; I think that some, if not all, of these new struct could be const, as elsewhere in this file. > + > +static struct cdns_reg_pairs ml_pcie_xcvr_diag_ln_regs[] = { > + {0x0100, XCVR_DIAG_HSCLK_SEL}, > + {0x0001, XCVR_DIAG_HSCLK_DIV}, > + {0x0812, XCVR_DIAG_PLLDRC_CTRL} > +}; ... CJ