From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S942876AbdAJDfT (ORCPT ); Mon, 9 Jan 2017 22:35:19 -0500 Received: from mail-by2nam01on0082.outbound.protection.outlook.com ([104.47.34.82]:48746 "EHLO NAM01-BY2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1162306AbdAJDfA (ORCPT ); Mon, 9 Jan 2017 22:35:00 -0500 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Suravee.Suthikulpanit@amd.com; From: Suravee Suthikulpanit To: , CC: , , , , Suravee Suthikulpanit , Suravee Suthikulpanit Subject: [PATCH v7 4/7] perf/amd/iommu: Declare pr_fmt and remove unnecessary pr_debug Date: Mon, 9 Jan 2017 21:33:44 -0600 Message-ID: <1484019227-11473-5-git-send-email-Suravee.Suthikulpanit@amd.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1484019227-11473-1-git-send-email-Suravee.Suthikulpanit@amd.com> References: <1484019227-11473-1-git-send-email-Suravee.Suthikulpanit@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [114.109.128.54] X-ClientProxiedBy: SG2PR04CA0045.apcprd04.prod.outlook.com (10.169.49.141) To CY4PR12MB1447.namprd12.prod.outlook.com (10.172.71.139) X-MS-Office365-Filtering-Correlation-Id: da5d601f-e7ee-4108-4bf7-08d43909a6d3 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001);SRVR:CY4PR12MB1447; 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Cc: Peter Zijlstra Cc: Borislav Petkov Signed-off-by: Suravee Suthikulpanit --- arch/x86/events/amd/iommu.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/x86/events/amd/iommu.c b/arch/x86/events/amd/iommu.c index 9744dc8..9bff41d 100644 --- a/arch/x86/events/amd/iommu.c +++ b/arch/x86/events/amd/iommu.c @@ -11,6 +11,8 @@ * published by the Free Software Foundation. */ +#define pr_fmt(fmt) "perf/amd_iommu: " fmt + #include #include #include @@ -288,7 +290,6 @@ static void perf_iommu_start(struct perf_event *event, int flags) u64 val; struct hw_perf_event *hwc = &event->hw; - pr_debug("perf: amd_iommu:perf_iommu_start\n"); if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED))) return; @@ -312,7 +313,6 @@ static void perf_iommu_read(struct perf_event *event) u64 cnt, prev; s64 delta; struct hw_perf_event *hwc = &event->hw; - pr_debug("perf: amd_iommu:perf_iommu_read\n"); if (amd_iommu_pc_get_counter(0, _GET_BANK(event), _GET_CNTR(event), &cnt)) return; @@ -339,8 +339,6 @@ static void perf_iommu_stop(struct perf_event *event, int flags) struct hw_perf_event *hwc = &event->hw; u64 config; - pr_debug("perf: amd_iommu:perf_iommu_stop\n"); - if (hwc->state & PERF_HES_UPTODATE) return; @@ -362,7 +360,6 @@ static int perf_iommu_add(struct perf_event *event, int flags) struct perf_amd_iommu *perf_iommu = container_of(event->pmu, struct perf_amd_iommu, pmu); - pr_debug("perf: amd_iommu:perf_iommu_add\n"); event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED; /* request an iommu bank/counter */ @@ -383,7 +380,6 @@ static void perf_iommu_del(struct perf_event *event, int flags) struct perf_amd_iommu *perf_iommu = container_of(event->pmu, struct perf_amd_iommu, pmu); - pr_debug("perf: amd_iommu:perf_iommu_del\n"); perf_iommu_stop(event, PERF_EF_UPDATE); /* clear the assigned iommu bank/counter */ @@ -443,7 +439,7 @@ static __init int _init_perf_amd_iommu( /* Init events attributes */ if (_init_events_attrs(perf_iommu) != 0) - pr_err("perf: amd_iommu: Only support raw events.\n"); + pr_err("Only support raw events.\n"); perf_iommu->max_banks = amd_iommu_pc_get_max_banks(0); perf_iommu->max_counters = amd_iommu_pc_get_max_counters(0); @@ -456,7 +452,7 @@ static __init int _init_perf_amd_iommu( ret = perf_pmu_register(&perf_iommu->pmu, name, -1); if (ret) { - pr_err("perf: amd_iommu: Failed to initialized.\n"); + pr_err("Error initializing AMD IOMMU perf counters.\n"); amd_iommu_pc_exit(); } else { pr_info("perf: amd_iommu: Detected. (%d banks, %d counters/bank)\n", -- 1.8.3.1