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Wed, 28 Aug 2024 09:31:55 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47S9Vsdv027169 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 28 Aug 2024 09:31:54 GMT Received: from [10.239.132.205] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 28 Aug 2024 02:31:49 -0700 Message-ID: <148451f2-6b1b-4616-b703-fd52e7afa2be@quicinc.com> Date: Wed, 28 Aug 2024 17:31:46 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 6/6] arm64: dts: qcom: add base QCS615 RIDE dts To: Krzysztof Kozlowski CC: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , , , , References: <20240828-add_initial_support_for_qcs615-v1-0-5599869ea10f@quicinc.com> <20240828-add_initial_support_for_qcs615-v1-6-5599869ea10f@quicinc.com> <22qkvfravm6sxiq3xfavahg2u6b2pwlyzqbqvd55zym5zef3gi@m4bsqkdvggty> <17d0017e-b55d-4b32-9fd3-1a1a84e5ebf9@quicinc.com> <0ec92d59-0648-40ed-a522-307152b5c37d@kernel.org> From: Lijuan Gao In-Reply-To: <0ec92d59-0648-40ed-a522-307152b5c37d@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: umurXFGdi-WOQN79eSibZz3mTJOXInt0 X-Proofpoint-ORIG-GUID: umurXFGdi-WOQN79eSibZz3mTJOXInt0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-28_03,2024-08-27_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 adultscore=0 malwarescore=0 suspectscore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 phishscore=0 lowpriorityscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408280068 在 8/28/2024 5:11 PM, Krzysztof Kozlowski 写道: > On 28/08/2024 09:54, Lijuan Gao wrote: >> >> >> 在 8/28/2024 2:25 PM, Krzysztof Kozlowski 写道: >>> On Wed, Aug 28, 2024 at 10:02:16AM +0800, Lijuan Gao wrote: >>>> Add initial support for Qualcomm QCS615 RIDE board and enable >>>> the QCS615 RIDE board to shell with dcc console. >>>> >>>> Signed-off-by: Lijuan Gao >>>> --- >>>> arch/arm64/boot/dts/qcom/Makefile | 1 + >>>> arch/arm64/boot/dts/qcom/qcs615-ride.dts | 15 +++++++++++++++ >>>> 2 files changed, 16 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile >>>> index 197ab325c0b9..c5503f189847 100644 >>>> --- a/arch/arm64/boot/dts/qcom/Makefile >>>> +++ b/arch/arm64/boot/dts/qcom/Makefile >>>> @@ -110,6 +110,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb >>>> dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb >>>> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb >>>> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb >>>> +dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride.dtb >>>> dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb >>>> dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb >>>> dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb >>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts >>>> new file mode 100644 >>>> index 000000000000..31d32ad951b5 >>>> --- /dev/null >>>> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts >>>> @@ -0,0 +1,15 @@ >>>> +// SPDX-License-Identifier: BSD-3-Clause >>>> +/* >>>> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. >>>> + */ >>>> +/dts-v1/; >>>> + >>>> +#include "qcs615.dtsi" >>>> +/ { >>>> + model = "Qualcomm Technologies, Inc. QCS615 Ride"; >>>> + compatible = "qcom,qcs615-ride", "qcom,qcs615"; >>>> + >>>> + chosen { >>>> + bootargs = "console=hvc0"; >>> >>> Noooo, last time I agreed on this, you told me later it is different. >>> >> In the early stages, enabling HVC is to more easily verify clock and >> PMIC related functions, as it’s difficult to debug without the console >> log. After the clock and PMIC are ready, we will enable the UART console. > > Working serial is supposed to be part of the early submission. > Okay, I will remove it in the next patch. > Best regards, > Krzysztof > > -- Thx and BRs Lijuan Gao