From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751915AbdARGCO (ORCPT ); Wed, 18 Jan 2017 01:02:14 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:30533 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751304AbdARGAp (ORCPT ); Wed, 18 Jan 2017 01:00:45 -0500 From: Chunfeng Yun To: Kishon Vijay Abraham I CC: Matthias Brugger , Felipe Balbi , Rob Herring , Mark Rutland , Ian Campbell , Chunfeng Yun , , , , , Subject: [RESEND PATCH 4/6] arm64: dts: mt8173: add a new reference clock for usb3 analog phy Date: Wed, 18 Jan 2017 14:00:12 +0800 Message-ID: <1484719214-11989-4-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1484719214-11989-1-git-send-email-chunfeng.yun@mediatek.com> References: <1484719214-11989-1-git-send-email-chunfeng.yun@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org add a new reference clock which comes from 26M oscillator directly for SuperSpeed analog phy. and the old one which comes for PLL is 48M for HighSpeed analog phy. Signed-off-by: Chunfeng Yun --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 12e7027..5d1663b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -754,8 +754,8 @@ u3phy: usb-phy@11290000 { compatible = "mediatek,mt8173-u3phy"; reg = <0 0x11290000 0 0x800>; - clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; - clock-names = "u3phya_ref"; + clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk26m>; + clock-names = "u2ref_clk", "u3ref_clk"; #address-cells = <2>; #size-cells = <2>; ranges; -- 1.7.9.5