From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751562AbdATGww (ORCPT ); Fri, 20 Jan 2017 01:52:52 -0500 Received: from mailout3.w1.samsung.com ([210.118.77.13]:55574 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751366AbdATGwm (ORCPT ); Fri, 20 Jan 2017 01:52:42 -0500 X-AuditID: cbfec7ef-f79d26d00000420c-f9-5881b3b09438 From: Andrzej Hajda To: Inki Dae , dri-devel@lists.freedesktop.org, Krzysztof Kozlowski Cc: Andrzej Hajda , Bartlomiej Zolnierkiewicz , Marek Szyprowski , Kyungmin Park , linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 0/7] drm/exynos: add Ultra HD and interlace modes support to Exynos5433 Date: Fri, 20 Jan 2017 07:52:18 +0100 Message-id: <1484895145-511-1-git-send-email-a.hajda@samsung.com> X-Mailer: git-send-email 2.7.4 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrEIsWRmVeSWpSXmKPExsWy7djP87obNjdGGPxewGJxa905VouNM9az Wlz5+p7NYtL9CSwW589vYLc42/SG3eLyrjlsFjPO72OyWHvkLrsDp8emVZ1sHve7jzN59G1Z xejxeZNcAEsUl01Kak5mWWqRvl0CV8ay3unsBYc4Kha9n8jewPiSrYuRk0NCwERizZ/XTBC2 mMSFe+uB4lwcQgLLGCWmvW1nhXA+M0p8u7aVHabjVMsEIJsDouoXVM1/RomPq6aB1bAJaEr8 3XwTbIOIQK7Eya9HwKYyC/xhlLh5ZykjSEJYIFLi1NLJLCA2i4CqxPIz28AaeAUcJQ7/fgp1 npzEzXOdzCDNEgL32SQuLjnMCLJZQkBWYtMBZogaF4kl51dB1QtLvDq+BepQGYnLk7tZIHq7 GSU+9Z9gh3CmMEr8+zADqtta4vDxi6wgNrMAn8SkbdOZIRbwSnS0CUGUeEjcbL8PNdRRYsPS x2C2kECsxLHdW9gnMEovYGRYxSiSWlqcm55abKhXnJhbXJqXrpecn7uJERizp/8df7+D8Wlz yCFGAQ5GJR7eHScaIoRYE8uKK3MPMUpwMCuJ8Pasb4wQ4k1JrKxKLcqPLyrNSS0+xCjNwaIk zrt3wZVwIYH0xJLU7NTUgtQimCwTB6dUAyPz6a9XWf3eyzKp6T3XTdKJmnJM1v2vlPMRrfjM P3UL51133pDhsKp1a7e2qXhaSdMp/9w3p9JYj7GWSZ5TPf1+8n/DiWZpjIvlBRdWMLX+Sd51 XUCd46vIgrv2lu5KO7wmNL8y//LounO3IWvo96w9iTtdBdjznDriJT3UN/P5Oxy50H9pihJL cUaioRZzUXEiAFH//DfVAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOLMWRmVeSWpSXmKPExsVy+t/xa7orNjdGGPy4IGZxa905VouNM9az Wlz5+p7NYtL9CSwW589vYLc42/SG3eLyrjlsFjPO72OyWHvkLrsDp8emVZ1sHve7jzN59G1Z xejxeZNcAEuUm01GamJKapFCal5yfkpmXrqtUmiIm66FkkJeYm6qrVKErm9IkJJCWWJOKZBn ZIAGHJwD3IOV9O0S3DKW9U5nLzjEUbHo/UT2BsaXbF2MnBwSAiYSp1omsEPYYhIX7q0HinNx CAksYZRYdXM+M4TTyCTx+MtSsA42AU2Jv5tvgtkiArkS65/OZAcpYhb4xyix4eobJpCEsECk xKmlk1lAbBYBVYnlZ7aBNfAKOEoc/v0UarWcxM1zncwTGLkXMDKsYhRJLS3OTc8tNtIrTswt Ls1L10vOz93ECAzUbcd+btnB2PUu+BCjAAejEg/vjhMNEUKsiWXFlbmHGCU4mJVEeHvWN0YI 8aYkVlalFuXHF5XmpBYfYjQFWj6RWUo0OR8YRXkl8YYmhuaWhkbGFhbmRkZK4rxTP1wJFxJI TyxJzU5NLUgtgulj4uCUamCMsF1V1ZnG0fmphb1q+YbPLo6/vm8OdRcUZ+uZJr8sy6pxw8e0 1W6/tx7c0ul+/PyFXz/3VgXfrGaNuW4qLVYbWnlctTxFaeZ0l68fSxrNXHh8ZGee//Pm8f/g lNfmxktCOjY6SbrPWHjdY3KgOvvTBvWXfeZ5Z8Kr/vM9P2dtVOOyTaL+/kUlluKMREMt5qLi RADIXUtwagIAAA== X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170120065229eucas1p22f0eed53220820b1145294029d4bd706 X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?UTF-8?B?QW5kcnplaiBIYWpkYRtTUlBPTC1LZXJuZWwgKFRQKRvsgrw=?= =?UTF-8?B?7ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?QW5kcnplaiBIYWpkYRtTUlBPTC1LZXJuZWwgKFRQKRtTYW1z?= =?UTF-8?B?dW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170120065229eucas1p22f0eed53220820b1145294029d4bd706 X-RootMTR: 20170120065229eucas1p22f0eed53220820b1145294029d4bd706 References: Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Inki, This patchset adds support for UltraHD and intrelace modes on DECON and HDMI drivers of Exynos5433 chipset. To fully support it on TM2(e) platforms MHL patches are alse required which will be posted in separate patchset. Krzysztof, DTS patch do not depend on the previous patches, so there is no need to synchronize branches. Regards Andrzej Andrzej Hajda (7): drm/exynos/hdmi: add 297MHz pixel clock support drm/exynos/hdmi: fix VSI infoframe registers drm/exynos/hdmi: fix PLL for 27MHz settings drm/exynos/hdmi: add bridge support drm/exynos/decon5433: add support for interlace modes drm/exynos/decon5433: signal vblank only on odd fields arm64: dts: exynos: configure TV path clocks for Ultra HD modes arch/arm64/boot/dts/exynos/exynos5433.dtsi | 3 + drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 52 ++++++++++++----- drivers/gpu/drm/exynos/exynos_hdmi.c | 80 +++++++++++++++++++++------ include/video/exynos5433_decon.h | 2 + 4 files changed, 107 insertions(+), 30 deletions(-) -- 2.7.4