From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750889AbdAWKGE (ORCPT ); Mon, 23 Jan 2017 05:06:04 -0500 Received: from mailout3.w1.samsung.com ([210.118.77.13]:9981 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750708AbdAWKGC (ORCPT ); Mon, 23 Jan 2017 05:06:02 -0500 X-AuditID: cbfec7f5-f79d06d000004445-11-5885d586e849 From: Andrzej Hajda To: Inki Dae , dri-devel@lists.freedesktop.org, Krzysztof Kozlowski Cc: Andrzej Hajda , Bartlomiej Zolnierkiewicz , Marek Szyprowski , Kyungmin Park , linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v3 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes Date: Mon, 23 Jan 2017 11:05:49 +0100 Message-id: <1485165949-32661-1-git-send-email-a.hajda@samsung.com> X-Mailer: git-send-email 2.7.4 In-reply-to: X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrAIsWRmVeSWpSXmKPExsWy7djP87ptV1sjDBbuE7K4te4cq8XGGetZ La58fc9mMen+BBaL8+c3sFucbXrDbnF51xw2ixnn9zFZrD1yl92B02PTqk42j/vdx5k8+ras YvT4vEkugCWKyyYlNSezLLVI3y6BK+Pgiz/sBU85Kx5uXc/UwLiRo4uRk0NCwETi95dzTBC2 mMSFe+vZuhi5OIQEljJKrD8ygRnC+cwo0b9xFjtMx+P+OSwQiWWMEtM+dzBCOP8ZJebs/skC UsUmoCnxd/NNNhBbRCBX4uTXI2BzmQX+MErcvLOUESQhLBApcXXCI7DlLAKqElte7AVq5uDg FXCWWHxbG2KbnMTNc53MIDangL3EpvuHwOZICPxmk9h3Yi47SL2EgKzEpgPMEPUuErOu/4Ky hSVeHd8CdbWMxOXJ3SwQvd2MEp/6T7BDOFMYJf59mAHVYS1x+PhFVhCbWYBPYtK26cwQC3gl OtqEIEo8JI72T2WBsB0lTj87CQ2wSUBDvzezTmCUWcDIsIpRJLW0ODc9tdhUrzgxt7g0L10v OT93EyMwnk//O/51B+PSY1aHGAU4GJV4eAWetkQIsSaWFVfmHmKU4GBWEuE9ebA1Qog3JbGy KrUoP76oNCe1+BCjNAeLkjjvngVXwoUE0hNLUrNTUwtSi2CyTBycUg2M/p3GDMvvu/rPb087 a5l77tN3h+/nn0dszDOZttYoVcnJTNJOOHMmtx5vXTdTxSXmI8Jh5p+/czfNWH7aesdym/or P4LXed0K2pbpeO7mRpYNBedSyjp6tgYvk55l2HDs5qcfs33Ue7kbt12p6kkMPzvNwVHnq10D p/ra4yl6ZY2bCjs+dRopsRRnJBpqMRcVJwIAo7L1kuMCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrHLMWRmVeSWpSXmKPExsVy+t/xa7pNV1sjDD5/5La4te4cq8XGGetZ La58fc9mMen+BBaL8+c3sFucbXrDbnF51xw2ixnn9zFZrD1yl92B02PTqk42j/vdx5k8+ras YvT4vEkugCXKzSYjNTEltUghNS85PyUzL91WKTTETddCSSEvMTfVVilC1zckSEmhLDGnFMgz MkADDs4B7sFK+nYJbhkHX/xhL3jKWfFw63qmBsaNHF2MnBwSAiYSj/vnsEDYYhIX7q1n62Lk 4hASWMIosXviXXYIp5FJ4vqOtWBVbAKaEn8332QDsUUEciXWP50JVsQs8I9RYsPVN0wgCWGB SIkV/V/BbBYBVYktL/YCNXNw8Ao4Syy+rQ2xTU7i5rlOZhCbU8BeYtP9Q2AzhQTsJJonfGWf wMi7gJFhFaNIamlxbnpusZFecWJucWleul5yfu4mRmBYbzv2c8sOxq53wYcYBTgYlXh4BZ62 RAixJpYVV+YeYpTgYFYS4T15sDVCiDclsbIqtSg/vqg0J7X4EKMp0E0TmaVEk/OBMZdXEm9o YmhuaWhkbGFhbmSkJM479cOVcCGB9MSS1OzU1ILUIpg+Jg5OqQbG+p4Hdl7OF2WmprWcThT+ dpix/FrxaaMj3367t63tybMTrI+zOX62fpvBhLddvLaHDbS9t3/NW3FZekvgIx6xx7kuon8u rX7wLD3IV7smJeL89009XBu7H//8mRrMeuzzXv2rnz8wv9XknGOfMKlFKsd/YvGhk/3Vj5bn 91R+FmIzdY+ZxZ2gxFKckWioxVxUnAgAe7kV0oECAAA= X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170123100557eucas1p28174748d64c4e8503a2006a9c5b554a6 X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?UTF-8?B?QW5kcnplaiBIYWpkYRtTUlBPTC1LZXJuZWwgKFRQKRvsgrw=?= =?UTF-8?B?7ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?QW5kcnplaiBIYWpkYRtTUlBPTC1LZXJuZWwgKFRQKRtTYW1z?= =?UTF-8?B?dW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170123100557eucas1p28174748d64c4e8503a2006a9c5b554a6 X-RootMTR: 20170123100557eucas1p28174748d64c4e8503a2006a9c5b554a6 References: Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Ultra HD modes requires clock ticking at increased rate. Signed-off-by: Andrzej Hajda --- v2: long lines wrapped v3: moved assigned clocks to cmu_disp node in tm2-common --- arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index cd8847b..5f1e172 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -217,6 +217,18 @@ assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>; }; +&cmu_disp { + assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, + <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; + assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, + <0>, + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; + assigned-clock-rates = <0>, <400000000>; +}; + &cmu_fsys { assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>, <&cmu_top CLK_MOUT_SCLK_USBHOST30>, -- 2.7.4