From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752325AbdBJHwF (ORCPT ); Fri, 10 Feb 2017 02:52:05 -0500 Received: from mail-pg0-f68.google.com ([74.125.83.68]:34688 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752103AbdBJHwD (ORCPT ); Fri, 10 Feb 2017 02:52:03 -0500 From: Chris Zhong To: dri-devel@lists.freedesktop.org, kishon@ti.com, robh@kernel.org, linux-rockchip@lists.infradead.org Cc: linux-kernel@vger.kernel.org, mark.yao@rock-chips.com, groeck@chromium.org, seanpaul@chromium.org, zyw@rock-chips.com, Heiko Stuebner , linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/4] phy: rockchip-typec: support DP phy switch Date: Fri, 10 Feb 2017 15:44:13 +0800 Message-Id: <1486712654-15431-4-git-send-email-zyw@rock-chips.com> X-Mailer: git-send-email 2.6.3 In-Reply-To: <1486712654-15431-1-git-send-email-zyw@rock-chips.com> References: <1486712654-15431-1-git-send-email-zyw@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There are 2 Type-c PHYs in RK3399, but only one DP controller. Hence only one PHY can connect to DP controller at one time, the other should be disconnected. The GRF_SOC_CON26 register has a switch bit to do it, set this bit means enable PHY 1, clear this bit means enable PHY 0. Signed-off-by: Chris Zhong --- drivers/phy/phy-rockchip-typec.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/phy/phy-rockchip-typec.c b/drivers/phy/phy-rockchip-typec.c index 7cfb0f8..1604aaa 100644 --- a/drivers/phy/phy-rockchip-typec.c +++ b/drivers/phy/phy-rockchip-typec.c @@ -267,6 +267,7 @@ struct rockchip_usb3phy_port_cfg { struct usb3phy_reg usb3tousb2_en; struct usb3phy_reg external_psm; struct usb3phy_reg pipe_status; + struct usb3phy_reg uphy_dp_sel; }; struct rockchip_typec_phy { @@ -736,6 +737,7 @@ static const struct phy_ops rockchip_usb3_phy_ops = { static int rockchip_dp_phy_power_on(struct phy *phy) { struct rockchip_typec_phy *tcphy = phy_get_drvdata(phy); + struct rockchip_usb3phy_port_cfg *cfg = &tcphy->port_cfgs; int new_mode, ret = 0; u32 val; @@ -766,6 +768,8 @@ static int rockchip_dp_phy_power_on(struct phy *phy) tcphy_phy_init(tcphy, new_mode); } + property_enable(tcphy, &cfg->uphy_dp_sel, 1); + ret = readx_poll_timeout(readl, tcphy->base + DP_MODE_CTL, val, val & DP_MODE_A2, 1000, PHY_MODE_SET_TIMEOUT); @@ -869,6 +873,11 @@ static int tcphy_parse_dt(struct rockchip_typec_phy *tcphy, if (ret) return ret; + ret = tcphy_get_param(dev, &cfg->uphy_dp_sel, + "rockchip,uphy-dp-sel"); + if (ret) + return ret; + tcphy->grf_regs = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); if (IS_ERR(tcphy->grf_regs)) { -- 2.6.3