From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751949AbdBOMAx (ORCPT ); Wed, 15 Feb 2017 07:00:53 -0500 Received: from mail-db5eur01on0079.outbound.protection.outlook.com ([104.47.2.79]:9600 "EHLO EUR01-DB5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751875AbdBOMAv (ORCPT ); Wed, 15 Feb 2017 07:00:51 -0500 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=andrei-tiberiu.breana@nxp.com; From: To: , CC: , , , , , , , , Tiberiu Breana Subject: [PATCH v2 2/2] ARM: imx: Add AXI address filter support for MMDC profiling Date: Wed, 15 Feb 2017 14:00:26 +0200 Message-ID: <1487160026-9376-3-git-send-email-andrei-tiberiu.breana@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487160026-9376-1-git-send-email-andrei-tiberiu.breana@nxp.com> References: <1487160026-9376-1-git-send-email-andrei-tiberiu.breana@nxp.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [192.88.146.1] X-ClientProxiedBy: AM4PR0902CA0020.eurprd09.prod.outlook.com (10.171.89.30) To DB5PR04MB1000.eurprd04.prod.outlook.com (10.161.199.139) X-MS-Office365-Filtering-Correlation-Id: a4175672-6286-4974-ce16-08d4559a47c3 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001)(48565401081);SRVR:DB5PR04MB1000; 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Signed-off-by: Tiberiu Breana --- arch/arm/mach-imx/mmdc.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c index 89a926f..7826289 100644 --- a/arch/arm/mach-imx/mmdc.c +++ b/arch/arm/mach-imx/mmdc.c @@ -1,4 +1,5 @@ /* + * Copyright 2017 NXP * Copyright 2011,2016 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * @@ -47,6 +48,7 @@ #define PROFILE_SEL 0x10 #define MMDC_MADPCR0 0x410 +#define MMDC_MADPCR1 0x414 #define MMDC_MADPSR0 0x418 #define MMDC_MADPSR1 0x41C #define MMDC_MADPSR2 0x420 @@ -57,6 +59,7 @@ #define MMDC_NUM_COUNTERS 6 #define MMDC_FLAG_PROFILE_SEL 0x1 +#define MMDC_PRF_AXI_ID_CLEAR 0x0 #define to_mmdc_pmu(p) container_of(p, struct mmdc_pmu, pmu) @@ -161,8 +164,11 @@ static struct attribute_group mmdc_pmu_events_attr_group = { }; PMU_FORMAT_ATTR(event, "config:0-63"); +PMU_FORMAT_ATTR(axi_id, "config1:0-63"); + static struct attribute *mmdc_pmu_format_attrs[] = { &format_attr_event.attr, + &format_attr_axi_id.attr, NULL, }; @@ -345,6 +351,14 @@ static void mmdc_pmu_event_start(struct perf_event *event, int flags) writel(DBG_RST, reg); + /* + * Write the AXI id parameter to MADPCR1. + */ + val = event->attr.config1; + reg = mmdc_base + MMDC_MADPCR1; + writel(val, reg); + + reg = mmdc_base + MMDC_MADPCR0; val = DBG_EN; if (pmu_mmdc->devtype_data->flags & MMDC_FLAG_PROFILE_SEL) val |= PROFILE_SEL; @@ -382,6 +396,10 @@ static void mmdc_pmu_event_stop(struct perf_event *event, int flags) reg = mmdc_base + MMDC_MADPCR0; writel(PRF_FRZ, reg); + + reg = mmdc_base + MMDC_MADPCR1; + writel(MMDC_PRF_AXI_ID_CLEAR, reg); + mmdc_pmu_event_update(event); } -- 2.7.4