From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932193AbdBVI41 (ORCPT ); Wed, 22 Feb 2017 03:56:27 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:55474 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1754544AbdBVIzW (ORCPT ); Wed, 22 Feb 2017 03:55:22 -0500 From: Chunfeng Yun To: Kishon Vijay Abraham I CC: Matthias Brugger , Felipe Balbi , Rob Herring , Mark Rutland , Ian Campbell , Chunfeng Yun , , , , , Subject: [PATCH v3 6/8] arm64: dts: mt8173: split usb SuperSpeed port into two ports Date: Wed, 22 Feb 2017 16:55:03 +0800 Message-ID: <1487753705-6745-6-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1487753705-6745-1-git-send-email-chunfeng.yun@mediatek.com> References: <1487753705-6745-1-git-send-email-chunfeng.yun@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org split the old SuperSpeed port node into a HighSpeed one and a new SuperSpeed one. Signed-off-by: Chunfeng Yun --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 12e7027..12c90e5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -724,8 +724,9 @@ <0 0x11280700 0 0x0100>; reg-names = "mac", "ippc"; interrupts = ; - phys = <&phy_port0 PHY_TYPE_USB3>, - <&phy_port1 PHY_TYPE_USB2>; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>, + <&u2port1 PHY_TYPE_USB2>; power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; clocks = <&topckgen CLK_TOP_USB30_SEL>, <&pericfg CLK_PERI_USB0>, @@ -761,14 +762,20 @@ ranges; status = "okay"; - phy_port0: port@11290800 { - reg = <0 0x11290800 0 0x800>; + u2port0: usb-phy@11290800 { + reg = <0 0x11290800 0 0x100>; #phy-cells = <1>; status = "okay"; }; - phy_port1: port@11291000 { - reg = <0 0x11291000 0 0x800>; + u3port0: usb-phy@11290900 { + reg = <0 0x11290900 0 0x700>; + #phy-cells = <1>; + status = "okay"; + }; + + u2port1: usb-phy@11291000 { + reg = <0 0x11291000 0 0x100>; #phy-cells = <1>; status = "okay"; }; -- 1.7.9.5