From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933188AbdBVPQm (ORCPT ); Wed, 22 Feb 2017 10:16:42 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:7997 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932928AbdBVPOY (ORCPT ); Wed, 22 Feb 2017 10:14:24 -0500 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 22 Feb 2017 07:12:45 -0800 From: Peter De Schrijver To: Peter De Schrijver , Prashant Gaikwad , Michael Turquette , "Stephen Boyd" , Stephen Warren , "Thierry Reding" , Alexandre Courbot , "Rob Herring" , Mark Rutland , "Rhyland Klein" , , , , Subject: [PATCH 0/7] Tegra210 clock bug fixes Date: Wed, 22 Feb 2017 17:13:55 +0200 Message-ID: <1487776444-4701-1-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.21.24.170] X-ClientProxiedBy: DRUKMAIL102.nvidia.com (10.25.59.20) To UKMAIL101.nvidia.com (10.26.138.13) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A number of bug fixes for the Tegra210 clock implementation. Peter De Schrijver (7): clk: tegra: fix pll_a1 iddq register, add pll_a1 clk: tegra: fix isp clock modelling clk: tegra: correct afi parent clk: tegra: remove non-existing pll_m_out1 clock clk: tegra: don't warn for PLL defaults unnecessarily clk: tegra: correct tegra210_pll_fixed_mdiv_cfg rate calculation clk: tegra: fix type for m field drivers/clk/tegra/clk-id.h | 1 + drivers/clk/tegra/clk-tegra-periph.c | 13 +++++++++--- drivers/clk/tegra/clk-tegra210.c | 35 ++++++++++++++++++++------------ drivers/clk/tegra/clk.h | 2 +- include/dt-bindings/clock/tegra210-car.h | 4 ++-- 5 files changed, 36 insertions(+), 19 deletions(-) -- 1.9.1