From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751390AbdBXJ0i (ORCPT ); Fri, 24 Feb 2017 04:26:38 -0500 Received: from mail-bl2nam02on0050.outbound.protection.outlook.com ([104.47.38.50]:39822 "EHLO NAM02-BL2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751173AbdBXJ0W (ORCPT ); Fri, 24 Feb 2017 04:26:22 -0500 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Suravee.Suthikulpanit@amd.com; From: Suravee Suthikulpanit To: , CC: , , , , Suravee Suthikulpanit Subject: [PATCH v11 02/10] perf/amd/iommu: Clean up bitwise operations Date: Fri, 24 Feb 2017 02:48:14 -0600 Message-ID: <1487926102-13073-3-git-send-email-Suravee.Suthikulpanit@amd.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1487926102-13073-1-git-send-email-Suravee.Suthikulpanit@amd.com> References: <1487926102-13073-1-git-send-email-Suravee.Suthikulpanit@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [114.109.128.54] X-ClientProxiedBy: HK2PR02CA0037.apcprd02.prod.outlook.com (10.163.104.175) To CY4PR12MB1447.namprd12.prod.outlook.com (10.172.71.139) X-MS-Office365-Filtering-Correlation-Id: 38284b1d-7544-4b66-182f-08d45c91fefd X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001)(48565401081);SRVR:CY4PR12MB1447; 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This should not affect logic and functionality. Cc: Peter Zijlstra Cc: Borislav Petkov Signed-off-by: Suravee Suthikulpanit --- arch/x86/events/amd/iommu.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/x86/events/amd/iommu.c b/arch/x86/events/amd/iommu.c index 8d8ed40..e112f49 100644 --- a/arch/x86/events/amd/iommu.c +++ b/arch/x86/events/amd/iommu.c @@ -164,11 +164,11 @@ static int get_next_avail_iommu_bnk_cntr(struct perf_amd_iommu *perf_iommu) for (bank = 0, shift = 0; bank < max_banks; bank++) { for (cntr = 0; cntr < max_cntrs; cntr++) { shift = bank + (bank*3) + cntr; - if (perf_iommu->cntr_assign_mask & (1ULL<cntr_assign_mask & BIT_ULL(shift)) { continue; } else { - perf_iommu->cntr_assign_mask |= (1ULL<cntr_assign_mask |= BIT_ULL(shift); + retval = ((bank & 0xFF) << 8) | (cntr & 0xFF); goto out; } } @@ -265,23 +265,23 @@ static void perf_iommu_enable_event(struct perf_event *ev) _GET_BANK(ev), _GET_CNTR(ev) , IOMMU_PC_COUNTER_SRC_REG, ®, true); - reg = 0ULL | devid | (_GET_DEVID_MASK(ev) << 32); + reg = devid | (_GET_DEVID_MASK(ev) << 32); if (reg) - reg |= (1UL << 31); + reg |= BIT(31); amd_iommu_pc_get_set_reg_val(devid, _GET_BANK(ev), _GET_CNTR(ev) , IOMMU_PC_DEVID_MATCH_REG, ®, true); - reg = 0ULL | _GET_PASID(ev) | (_GET_PASID_MASK(ev) << 32); + reg = _GET_PASID(ev) | (_GET_PASID_MASK(ev) << 32); if (reg) - reg |= (1UL << 31); + reg |= BIT(31); amd_iommu_pc_get_set_reg_val(devid, _GET_BANK(ev), _GET_CNTR(ev) , IOMMU_PC_PASID_MATCH_REG, ®, true); - reg = 0ULL | _GET_DOMID(ev) | (_GET_DOMID_MASK(ev) << 32); + reg = _GET_DOMID(ev) | (_GET_DOMID_MASK(ev) << 32); if (reg) - reg |= (1UL << 31); + reg |= BIT(31); amd_iommu_pc_get_set_reg_val(devid, _GET_BANK(ev), _GET_CNTR(ev) , IOMMU_PC_DOMID_MATCH_REG, ®, true); -- 1.8.3.1