From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751739AbdCCLc4 (ORCPT ); Fri, 3 Mar 2017 06:32:56 -0500 Received: from smtprelay4.synopsys.com ([198.182.47.9]:39634 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751333AbdCCLcv (ORCPT ); Fri, 3 Mar 2017 06:32:51 -0500 From: Vlad Zakharov To: linux-snps-arc@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vineet Gupta , Rob Herring , Vlad Zakharov Subject: [PATCH 2/3] ARC: [dts] add cpu nodes to ARCHS SMP device tree Date: Fri, 3 Mar 2017 14:30:01 +0300 Message-Id: <1488540602-11438-3-git-send-email-vzakhar@synopsys.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488540602-11438-1-git-send-email-vzakhar@synopsys.com> References: <1488540602-11438-1-git-send-email-vzakhar@synopsys.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Trying to get clock for CPU cores on SMP systems I found that I was only able to get clock for core[0]. That was because only one cpu@0 node was represented in ARC HS device tree and it was impossible to get clock for "non-existing" cores. So as ARC HS may have up to 4 cores we update device tree to match maximum possible cores quantity. Signed-off-by: Vlad Zakharov --- arch/arc/boot/dts/skeleton_hs_idu.dtsi | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/arc/boot/dts/skeleton_hs_idu.dtsi b/arch/arc/boot/dts/skeleton_hs_idu.dtsi index 662c5e0..54b277d 100644 --- a/arch/arc/boot/dts/skeleton_hs_idu.dtsi +++ b/arch/arc/boot/dts/skeleton_hs_idu.dtsi @@ -19,10 +19,28 @@ cpu@0 { device_type = "cpu"; - compatible = "snps,archs38xN"; + compatible = "snps,archs38"; reg = <0>; clocks = <&core_clk>; }; + cpu@1 { + device_type = "cpu"; + compatible = "snps,archs38"; + reg = <1>; + clocks = <&core_clk>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "snps,archs38"; + reg = <2>; + clocks = <&core_clk>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "snps,archs38"; + reg = <3>; + clocks = <&core_clk>; + }; }; /* TIMER0 with interrupt for clockevent */ -- 2.7.4