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[86.188.11.239]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483bd75df90sm246321165e9.14.2026.02.27.14.06.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Feb 2026 14:06:47 -0800 (PST) Message-ID: <148be140e22947a1f3524f24d8f55218650d3f2e.camel@linaro.org> Subject: Re: [PATCH v8 13/18] arm64: dts: qcom: x1e80100-crd: Add ov08x40 RGB sensor on CSIPHY4 From: Christopher Obbard To: Bryan O'Donoghue , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Konrad Dybcio , Vladimir Zapolskiy , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Krzysztof Kozlowski Date: Fri, 27 Feb 2026 22:06:46 +0000 In-Reply-To: <20260225-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v8-13-95517393bcb2@linaro.org> References: <20260225-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v8-0-95517393bcb2@linaro.org> <20260225-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v8-13-95517393bcb2@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-8 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi Bryan, On Wed, 2026-02-25 at 15:11 +0000, Bryan O'Donoghue wrote: > Define ov08x40 on cci1_i2c1. The RGB sensor appears on the AON CCI pins > connected to CSIPHY4 in four lane mode. >=20 > Signed-off-by: Bryan O'Donoghue > --- Reviewed-by: Christopher Obbard > arch/arm64/boot/dts/qcom/x1-crd.dtsi | 76 ++++++++++++++++++++++++++++++= ++++++ > 1 file changed, 76 insertions(+) >=20 > diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/q= com/x1-crd.dtsi > index c89f5ad0aed56..d47404c71b80b 100644 > --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi > @@ -6,6 +6,7 @@ > #include > #include > #include > +#include > #include > #include > =20 > @@ -901,6 +902,65 @@ &gpu { > status =3D "okay"; > }; > =20 > +&camss { > + status =3D "okay"; > + > + ports { > + /* > + * port0 =3D> csiphy0 > + * port1 =3D> csiphy1 > + * port2 =3D> csiphy2 > + * port3 =3D> csiphy4 > + */ > + port@3 { > + camss_csiphy4_inep0: endpoint@0 { > + clock-lanes =3D <7>; > + data-lanes =3D <0 1 2 3>; > + remote-endpoint =3D <&ov08x40_ep>; > + }; > + }; > + }; > +}; > + > +&cci1 { > + status =3D "okay"; > +}; > + > +&cci1_i2c1 { > + camera@36 { > + compatible =3D "ovti,ov08x40"; > + reg =3D <0x36>; > + > + reset-gpios =3D <&tlmm 237 GPIO_ACTIVE_LOW>; > + pinctrl-0 =3D <&cam_rgb_default>; > + pinctrl-names =3D "default"; > + > + clocks =3D <&camcc CAM_CC_MCLK4_CLK>; > + assigned-clocks =3D <&camcc CAM_CC_MCLK4_CLK>; > + assigned-clock-rates =3D <19200000>; > + > + orientation =3D <0>; /* front facing */ > + > + avdd-supply =3D <&vreg_l7b_2p8>; > + dovdd-supply =3D <&vreg_l3m_1p8>; > + > + port { > + ov08x40_ep: endpoint { > + data-lanes =3D <1 2 3 4>; > + link-frequencies =3D /bits/ 64 <400000000>; > + remote-endpoint =3D <&camss_csiphy4_inep0>; > + }; > + }; > + }; > +}; > + > +&csiphy4 { > + vdda-0p8-supply =3D <&vreg_l2c_0p8>; > + vdda-1p2-supply =3D <&vreg_l1c_1p2>; > + > + status =3D "okay"; > +}; > + > &i2c0 { > clock-frequency =3D <400000>; > =20 > @@ -1515,6 +1575,22 @@ &tlmm { > <44 4>, /* SPI (TPM) */ > <238 1>; /* UFS Reset */ > =20 > + cam_rgb_default: cam-rgb-default-state { > + mclk-pins { > + pins =3D "gpio100"; > + function =3D "cam_aon"; > + drive-strength =3D <16>; > + bias-disable; > + }; > + > + reset-n-pins { > + pins =3D "gpio237"; > + function =3D "gpio"; > + drive-strength =3D <2>; > + bias-disable; > + }; > + }; > + > edp_reg_en: edp-reg-en-state { > pins =3D "gpio70"; > function =3D "gpio";