From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758465AbdCUXd2 (ORCPT ); Tue, 21 Mar 2017 19:33:28 -0400 Received: from mail-pf0-f180.google.com ([209.85.192.180]:33564 "EHLO mail-pf0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758439AbdCUXd0 (ORCPT ); Tue, 21 Mar 2017 19:33:26 -0400 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 To: Jerome Brunet , "Stephen Boyd" , "Kevin Hilman" , "Carlo Caione" From: Michael Turquette In-Reply-To: <20170309104154.28295-4-jbrunet@baylibre.com> Cc: "Jerome Brunet" , linux-clk@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org References: <20170309104154.28295-1-jbrunet@baylibre.com> <20170309104154.28295-4-jbrunet@baylibre.com> Message-ID: <149013781178.54062.3390528282967464997@resonance> User-Agent: alot/0.3.7 Subject: Re: [PATCH v2 3/9] clk: meson8b: put dividers and muxes in tables Date: Tue, 21 Mar 2017 16:10:11 -0700 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id v2LNYMp1026842 Quoting Jerome Brunet (2017-03-09 02:41:48) > Until now, there was only 1 divider and 1 mux declared for the meson8b > platform. With the ongoing work on various system, including audio, this > is about to change. Use the same approach as gates for dividers and muxes, > putting them in tables to fix the register address at runtime. > > Signed-off-by: Jerome Brunet Looks good to me. Regards, Mike > --- > drivers/clk/meson/meson8b.c | 22 ++++++++++++++++++---- > 1 file changed, 18 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c > index d1cc4d7cc8ff..2937443d4505 100644 > --- a/drivers/clk/meson/meson8b.c > +++ b/drivers/clk/meson/meson8b.c > @@ -582,6 +582,14 @@ static struct clk_gate *const meson8b_clk_gates[] = { > &meson8b_ao_iface, > }; > > +static struct clk_mux *const meson8b_clk_muxes[] = { > + &meson8b_mpeg_clk_sel, > +}; > + > +static struct clk_divider *const meson8b_clk_dividers[] = { > + &meson8b_mpeg_clk_div, > +}; > + > static int meson8b_clkc_probe(struct platform_device *pdev) > { > void __iomem *clk_base; > @@ -604,15 +612,21 @@ static int meson8b_clkc_probe(struct platform_device *pdev) > /* Populate the base address for CPU clk */ > meson8b_cpu_clk.base = clk_base; > > - /* Populate the base address for the MPEG clks */ > - meson8b_mpeg_clk_sel.reg = clk_base + (u32)meson8b_mpeg_clk_sel.reg; > - meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg; > - > /* Populate base address for gates */ > for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++) > meson8b_clk_gates[i]->reg = clk_base + > (u32)meson8b_clk_gates[i]->reg; > > + /* Populate base address for muxes */ > + for (i = 0; i < ARRAY_SIZE(meson8b_clk_muxes); i++) > + meson8b_clk_muxes[i]->reg = clk_base + > + (u32)meson8b_clk_muxes[i]->reg; > + > + /* Populate base address for dividers */ > + for (i = 0; i < ARRAY_SIZE(meson8b_clk_dividers); i++) > + meson8b_clk_dividers[i]->reg = clk_base + > + (u32)meson8b_clk_dividers[i]->reg; > + > /* > * register all clks > * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1 > -- > 2.9.3 >