From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934571AbdCVNFg (ORCPT ); Wed, 22 Mar 2017 09:05:36 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:13493 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759401AbdCVNE7 (ORCPT ); Wed, 22 Mar 2017 09:04:59 -0400 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 22 Mar 2017 05:58:20 -0700 From: Peter De Schrijver To: Peter De Schrijver , Philipp Zabel , Rob Herring , Mark Rutland , Thierry Reding , "Jonathan Hunter" , , , Subject: [PATCH] clk: tegra: Add UARTB reset Date: Wed, 22 Mar 2017 14:58:12 +0200 Message-ID: <1490187493-6162-1-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.21.24.170] X-ClientProxiedBy: UKMAIL101.nvidia.com (10.26.138.13) To UKMAIL101.nvidia.com (10.26.138.13) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Bit 7 of CLK_RST_CONTROLLER_RST_DEVICES_L_0 controls the UARTB reset. Despite the fact that Tegra210 doesn't have VFIR, 224 was assigned as the clock ID for UARTB. We can't use 224 as the reset ID because that's already used for TEGRA210_RST_DFLL_DVCO. Signed-off-by: Peter De Schrijver --- include/dt-bindings/reset/tegra210-car.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/reset/tegra210-car.h b/include/dt-bindings/reset/tegra210-car.h index 296ec6e..de2fce4 100644 --- a/include/dt-bindings/reset/tegra210-car.h +++ b/include/dt-bindings/reset/tegra210-car.h @@ -6,6 +6,8 @@ #ifndef _DT_BINDINGS_RESET_TEGRA210_CAR_H #define _DT_BINDINGS_RESET_TEGRA210_CAR_H +#define TEGRA210_RST_UARTB 7 + #define TEGRA210_RESET(x) (7 * 32 + (x)) #define TEGRA210_RST_DFLL_DVCO TEGRA210_RESET(0) #define TEGRA210_RST_ADSP TEGRA210_RESET(1) -- 1.9.1