From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756107AbdDFKtw (ORCPT ); Thu, 6 Apr 2017 06:49:52 -0400 Received: from mailgw01.mediatek.com ([218.249.47.110]:55406 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1755415AbdDFKtp (ORCPT ); Thu, 6 Apr 2017 06:49:45 -0400 Message-ID: <1491475779.19361.4.camel@mhfsdcap03> Subject: Re: [PATCH v5 1/9] phy: phy-mt65xx-usb3: improve RX detection stable time From: Chunfeng Yun To: Kishon Vijay Abraham I CC: Matthias Brugger , Felipe Balbi , Rob Herring , "Mark Rutland" , Ian Campbell , , , , , Date: Thu, 6 Apr 2017 18:49:39 +0800 In-Reply-To: References: <1490945735-9531-1-git-send-email-chunfeng.yun@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2017-04-06 at 15:58 +0530, Kishon Vijay Abraham I wrote: > > On Friday 31 March 2017 01:05 PM, Chunfeng Yun wrote: > > The default value of RX detection stable time is 10us, and this > > margin is too big for some critical cases which cause U3 link fail > > and link to U2(probability is about 1%). So change it to 5us. > > > merged all the phy patches in this series to linux-phy -next. Thanks a lot > > Thanks > Kishon > > > Signed-off-by: Chunfeng Yun > > --- > > drivers/phy/phy-mt65xx-usb3.c | 18 ++++++++++++++++++ > > 1 file changed, 18 insertions(+) > > > > diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c > > index d972067..fe2392a 100644 > > --- a/drivers/phy/phy-mt65xx-usb3.c > > +++ b/drivers/phy/phy-mt65xx-usb3.c > > @@ -112,6 +112,14 @@ > > #define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8) > > #define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8) > > > > +#define U3P_U3_PHYD_RXDET1 (SSUSB_SIFSLV_U3PHYD_BASE + 0x128) > > +#define P3D_RG_RXDET_STB2_SET GENMASK(17, 9) > > +#define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9) > > + > > +#define U3P_U3_PHYD_RXDET2 (SSUSB_SIFSLV_U3PHYD_BASE + 0x12c) > > +#define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0) > > +#define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x)) > > + > > #define U3P_XTALCTL3 (SSUSB_SIFSLV_SPLLC + 0x0018) > > #define XC3_RG_U3_XTAL_RX_PWD BIT(9) > > #define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8) > > @@ -295,6 +303,16 @@ static void phy_instance_init(struct mt65xx_u3phy *u3phy, > > tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3); > > writel(tmp, port_base + U3P_PHYD_CDR1); > > > > + tmp = readl(port_base + U3P_U3_PHYD_RXDET1); > > + tmp &= ~P3D_RG_RXDET_STB2_SET; > > + tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10); > > + writel(tmp, port_base + U3P_U3_PHYD_RXDET1); > > + > > + tmp = readl(port_base + U3P_U3_PHYD_RXDET2); > > + tmp &= ~P3D_RG_RXDET_STB2_SET_P3; > > + tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10); > > + writel(tmp, port_base + U3P_U3_PHYD_RXDET2); > > + > > dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index); > > } > > > >