From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934326AbdDGPLE (ORCPT ); Fri, 7 Apr 2017 11:11:04 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:60773 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1756212AbdDGPKx (ORCPT ); Fri, 7 Apr 2017 11:10:53 -0400 From: Alexandre TORGUE To: Linus Walleij , Maxime Coquelin , Patrice Chotard , Paul Gortmaker , Rob Herring CC: , , , Subject: [PATCH 1/4] pinctrl: stm32: set pin to gpio input when used as interrupt Date: Fri, 7 Apr 2017 17:10:08 +0200 Message-ID: <1491577811-26989-2-git-send-email-alexandre.torgue@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1491577811-26989-1-git-send-email-alexandre.torgue@st.com> References: <1491577811-26989-1-git-send-email-alexandre.torgue@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG7NODE3.st.com (10.75.127.21) To SFHDAG3NODE2.st.com (10.75.127.8) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-04-07_12:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch ensures that pin is correctly set as gpio input when it is used as an interrupt. Signed-off-by: Alexandre TORGUE diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index abc405b..c8825e5 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -207,12 +207,35 @@ static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) .to_irq = stm32_gpio_to_irq, }; +static int stm32_gpio_irq_request_resources(struct irq_data *irq_data) +{ + struct stm32_gpio_bank *bank = irq_data->domain->host_data; + u32 ret; + + if (!gpiochip_is_requested(&bank->gpio_chip, irq_data->hwirq)) { + ret = stm32_gpio_request(&bank->gpio_chip, irq_data->hwirq); + if (ret) + return ret; + } + + return stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); +} + +static void stm32_gpio_irq_release_resources(struct irq_data *irq_data) +{ + struct stm32_gpio_bank *bank = irq_data->domain->host_data; + + stm32_gpio_free(&bank->gpio_chip, irq_data->hwirq); +} + static struct irq_chip stm32_gpio_irq_chip = { .name = "stm32gpio", .irq_eoi = irq_chip_eoi_parent, .irq_mask = irq_chip_mask_parent, .irq_unmask = irq_chip_unmask_parent, .irq_set_type = irq_chip_set_type_parent, + .irq_request_resources = stm32_gpio_irq_request_resources, + .irq_release_resources = stm32_gpio_irq_release_resources, }; static int stm32_gpio_domain_translate(struct irq_domain *d, -- 1.9.1