From: Geetha sowjanya <gakula@caviumnetworks.com>
To: will.deacon@arm.com, robin.murphy@arm.com,
lorenzo.pieralisi@arm.com, hanjun.guo@linaro.org,
sudeep.holla@arm.com, iommu@lists.linux-foundation.org
Cc: jcm@redhat.com, linux-kernel@vger.kernel.org,
robert.richter@cavium.com, catalin.marinas@arm.com,
sgoutham@cavium.com, linux-arm-kernel@lists.infradead.org,
linux-acpi@vger.kernel.org, geethasowjanya.akula@gmail.com,
linu.cherian@cavium.com, Geetha <gakula@cavium.com>
Subject: [PATCH 1/3] arm64: Add MIDR values for Cavium cn99xx SoCs
Date: Thu, 27 Apr 2017 17:16:22 +0530 [thread overview]
Message-ID: <1493293584-20287-2-git-send-email-gakula@caviumnetworks.com> (raw)
In-Reply-To: <1493293584-20287-1-git-send-email-gakula@caviumnetworks.com>
From: Geetha <gakula@cavium.com>
Add MIDR values for Cavium cn99xx SoCs
Signed-off-by: Geetha <gakula@cavium.com>
---
arch/arm64/include/asm/cputype.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index fc50271..066fad0 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -85,6 +85,7 @@
#define CAVIUM_CPU_PART_THUNDERX 0x0A1
#define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
+#define CAVIUM_CPU_PART_THUNDERX_99XX 0x0AF
#define BRCM_CPU_PART_VULCAN 0x516
@@ -94,6 +95,8 @@
#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
+#define MIDR_THUNDERX_99XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_99XX)
+#define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
#ifndef __ASSEMBLY__
--
1.9.1
next prev parent reply other threads:[~2017-04-27 12:05 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-27 11:46 [PATCH 0/3] Cavium ThunderX2 SMMUv3 errata workarounds Geetha sowjanya
2017-04-27 11:46 ` Geetha sowjanya [this message]
2017-04-27 13:01 ` [PATCH 1/3] arm64: Add MIDR values for Cavium cn99xx SoCs Jayachandran C.
2017-04-27 11:46 ` [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74 Geetha sowjanya
2017-04-27 16:42 ` Mark Rutland
2017-04-27 17:00 ` Will Deacon
2017-05-02 6:31 ` Geetha Akula
2017-05-03 9:47 ` Will Deacon
2017-05-03 10:32 ` Geetha Akula
2017-05-04 23:36 ` Jon Masters
2017-04-27 11:46 ` [PATCH 3/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 Geetha sowjanya
2017-04-27 13:39 ` [PATCH 0/3] Cavium ThunderX2 SMMUv3 errata workarounds Robert Richter
2017-04-27 16:37 ` Sunil Kovvuri
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