[PATCH 3/3] irqchip/mbigen: Fix the clear register offset

[Hanjun Guo <guohanjun@huawei.com>]

From: MaJun <majun258@huawei.com>

Don't minus reserved interrupts (64) when get the clear
register offset, because the clear register space includes
the space of these 64 interrupts.

This bug wasn't discovered until we running the driver on
a new platform with an updated firmware. It turns out that
there is a timeout mechanism to clear the register in the
mbigen which is for debug purpose and should be turned off,
but because of configuration mistake in firmware, this
function was turned on and covered up the bug in clear offset
calculate, it's time to fix it now.

Fixes: a6c2f87b8820 ("irqchip/mbigen: Implement the mbigen irq chip operation functions")
Signed-off-by: MaJun <majun258@huawei.com>
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
---
 drivers/irqchip/irq-mbigen.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c
index 167cdb5..295c2a0 100644
--- a/drivers/irqchip/irq-mbigen.c
+++ b/drivers/irqchip/irq-mbigen.c
@@ -106,10 +106,7 @@ static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
 static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq,
 					u32 *mask, u32 *addr)
 {
-	unsigned int ofst;
-
-	hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
-	ofst = hwirq / 32 * 4;
+	unsigned int ofst = hwirq / 32 * 4;
 
 	*mask = 1 << (hwirq % 32);
 	*addr = ofst + REG_MBIGEN_CLEAR_OFFSET;
-- 
1.7.12.4