From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753074AbdEIMEI (ORCPT ); Tue, 9 May 2017 08:04:08 -0400 Received: from mail-bn3nam01on0042.outbound.protection.outlook.com ([104.47.33.42]:64640 "EHLO NAM01-BN3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751360AbdEIMEG (ORCPT ); Tue, 9 May 2017 08:04:06 -0400 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Geethasowjanya.Akula@cavium.com; From: Geetha sowjanya To: will.deacon@arm.com, robin.murphy@arm.com, lorenzo.pieralisi@arm.com, hanjun.guo@linaro.org, sudeep.holla@arm.com, iommu@lists.linux-foundation.org Cc: jcm@redhat.com, linux-kernel@vger.kernel.org, robert.richter@cavium.com, catalin.marinas@arm.com, sgoutham@cavium.com, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, geethasowjanya.akula@gmail.com, linu.cherian@cavium.com, Charles.Garcia-Tobin@arm.com Subject: [v4 0/4] Cavium ThunderX2 SMMUv3 errata workarounds Date: Tue, 9 May 2017 17:15:10 +0530 Message-Id: <1494330314-30179-1-git-send-email-gakula@caviumnetworks.com> X-Mailer: git-send-email 1.7.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [14.140.2.178] X-ClientProxiedBy: MA1PR01CA0099.INDPRD01.PROD.OUTLOOK.COM (10.174.56.143) To BY2PR0701MB2024.namprd07.prod.outlook.com (10.163.156.139) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2580a273-0f9a-41ca-7d8f-08d496d37bc4 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001)(201703131423075)(201703031133081);SRVR:BY2PR0701MB2024; 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Errata ID #74 SMMU register alias Page 1 is not implemented 2. Errata ID #126 SMMU doesnt support unique IRQ lines and also MSI for gerror, eventq and cmdq-sync The following patchset does software workaround for these two erratas. This series is based on patchset. https://www.spinics.net/lists/arm-kernel/msg578443.html Changes from v3: - Merged patches 1, 2 and 4 of Version 3. - Modified the page1_offset_adjust() and get_irq_flags() implementation as suggested by Robin. Changes from v2: Updated "Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt" document with new SMMU option used to enable errata workaround. Changes from v1: Since the use of MIDR register is rejected and SMMU_IIDR is broken on this silicon, as suggested by Will Deacon modified the patches to use ThunderX2 SMMUv3 IORT model number to enable errata workaround. Geetha Sowjanya (1): iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126 Linu Cherian (3): ACPICA: IORT: Add Cavium ThunderX2 SMMUv3 model definition. ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74 Documentation/arm64/silicon-errata.txt | 2 + .../devicetree/bindings/iommu/arm,smmu-v3.txt | 6 ++ drivers/acpi/arm64/iort.c | 10 +- drivers/iommu/arm-smmu-v3.c | 109 ++++++++++++++++----- include/acpi/actbl2.h | 2 + 5 files changed, 103 insertions(+), 26 deletions(-) -- 1.8.3.1