From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759487AbdEOHt2 (ORCPT ); Mon, 15 May 2017 03:49:28 -0400 Received: from mail-dm3nam03on0044.outbound.protection.outlook.com ([104.47.41.44]:14304 "EHLO NAM03-DM3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1759303AbdEOHtX (ORCPT ); Mon, 15 May 2017 03:49:23 -0400 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=fail action=none header.from=nxp.com; From: Dong Aisheng To: CC: , , , , , , , , , Dong Aisheng , Subject: [PATCH V2 3/6] dt-bindings: serial: fsl-lpuart: add i.MX7ULP support Date: Mon, 15 May 2017 15:48:56 +0800 Message-ID: <1494834539-17523-4-git-send-email-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1494834539-17523-1-git-send-email-aisheng.dong@nxp.com> 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X-Microsoft-Exchange-Diagnostics: 1;BL2PR03MB161;7:akzLK7+Y6fJJqadLFoWfkv3XUQq0yNCHfSO16Z4TDDhF5Y+ol6xruwKNelff03rqzjZXHiNdveBOwQwjg/uG9s23S1nAfq0rs9Tiay58pEF1Xk7lcy6Nv26c0rhvYEf9jRkXWXQIkgHUqA2kYQWxP3pqrJSE5lzamdGDSFQGpGaeFCyj74ALR56tGu8o2q9HX7ZN83XHMYqZCuHVEMq6rqEVNfzB6iaJ1IaDxVPHOond0jg6ATrngFlubAULJwG4g4GqIRY2uWcOmcD7WD1VFK0iVsjii3r42lAN1x5wOhq/SCDcvWe29vVgS+hwHF0XR+sMMnS04tg3M9mlB7BfCA== X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 May 2017 07:49:11.3997 (UTC) X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;Ip=[192.88.168.50];Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2PR03MB161 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The lpuart of imx7ulp is basically the same as ls1021a. It's also 32 bit width register, but unlike ls1021a, it's little endian. Besides that, imx7ulp lpuart has a minor different register layout from ls1021a. Cc: devicetree@vger.kernel.org Cc: Greg Kroah-Hartman Cc: Jiri Slaby Cc: Stefan Agner Cc: Mingkai Hu Cc: Yangbo Lu Acked-by: Rob Herring Acked-by: Fugang Duan Signed-off-by: Dong Aisheng --- Documentation/devicetree/bindings/serial/fsl-lpuart.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt index c95005e..a1252a0 100644 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt @@ -6,6 +6,8 @@ Required properties: on Vybrid vf610 SoC with 8-bit register organization - "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated on LS1021A SoC with 32-bit big-endian register organization + - "fsl,imx7ulp-lpuart" for lpuart compatible with the one integrated + on i.MX7ULP SoC with 32-bit little-endian register organization - reg : Address and length of the register set for the device - interrupts : Should contain uart interrupt - clocks : phandle + clock specifier pairs, one for each entry in clock-names -- 2.7.4