From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965283AbdEON70 (ORCPT ); Mon, 15 May 2017 09:59:26 -0400 Received: from mail-by2nam03on0066.outbound.protection.outlook.com ([104.47.42.66]:28416 "EHLO NAM03-BY2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S965239AbdEON7W (ORCPT ); Mon, 15 May 2017 09:59:22 -0400 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed) header.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com; From: Dong Aisheng To: CC: , , , , , , , Dong Aisheng Subject: [PATCH 0/9] clk: add imx7ulp clk support Date: Mon, 15 May 2017 21:59:14 +0800 Message-ID: <1494856763-6543-1-git-send-email-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.7.4 X-EOPAttributedMessage: 0 X-Matching-Connectors: 131393303597164895;(91ab9b29-cfa4-454e-5278-08d120cd25b8);() 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System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks The clocking scheme provides clear separation between M4 domain and A7 domain. Except for a few clock sources shared between two domains, such as the System Oscillator clock, the Slow IRC (SIRC), and and the Fast IRC clock (FIRCLK), clock sources and clock management are separated and contained within each domain. M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. Note: this series only adds A7 clock domain support as M4 clock domain will be handled by M4 seperately. Dong Aisheng (9): clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support clk: reparent orphans after critical clocks enabled clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support clk: imx: add pllv4 support clk: imx: add pfdv2 support clk: imx: add composite clk support dt-bindings: clock: add imx7ulp clock binding doc clk: imx: make mux parent strings const clk: imx: add imx7ulp clk driver .../devicetree/bindings/clock/imx7ulp-clock.txt | 62 +++++++ drivers/clk/clk-divider.c | 2 + drivers/clk/clk-fractional-divider.c | 10 ++ drivers/clk/clk.c | 39 ++-- drivers/clk/imx/Makefile | 6 +- drivers/clk/imx/clk-busy.c | 2 +- drivers/clk/imx/clk-composite.c | 93 ++++++++++ drivers/clk/imx/clk-fixup-mux.c | 2 +- drivers/clk/imx/clk-imx7ulp.c | 171 ++++++++++++++++++ drivers/clk/imx/clk-pfdv2.c | 199 +++++++++++++++++++++ drivers/clk/imx/clk-pllv4.c | 196 ++++++++++++++++++++ drivers/clk/imx/clk.h | 31 +++- include/dt-bindings/clock/imx7ulp-clock.h | 108 +++++++++++ include/linux/clk-provider.h | 11 ++ 14 files changed, 902 insertions(+), 30 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/imx7ulp-clock.txt create mode 100644 drivers/clk/imx/clk-composite.c create mode 100644 drivers/clk/imx/clk-imx7ulp.c create mode 100644 drivers/clk/imx/clk-pfdv2.c create mode 100644 drivers/clk/imx/clk-pllv4.c create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h -- 2.7.4