From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932200AbdEQSX4 (ORCPT ); Wed, 17 May 2017 14:23:56 -0400 Received: from mail-out.m-online.net ([212.18.0.10]:52205 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932156AbdEQSXv (ORCPT ); Wed, 17 May 2017 14:23:51 -0400 X-Auth-Info: shq0OBm6dBi/K5e5JyWS1LOfjP3x1eA1eTylVpg8IvQ= From: Anatolij Gustschin To: stillcompiling@gmail.com, joshua.clayton@uniwest.com, bst@pengutronix.de Cc: linux-fpga@vger.kernel.org, atull@kernel.org, moritz.fischer@ettus.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com Subject: [PATCH v10 3/3] ARM: dts: imx6q-evi: support cyclone-ps-spi Date: Wed, 17 May 2017 20:23:42 +0200 Message-Id: <1495045422-19183-3-git-send-email-agust@denx.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495045422-19183-1-git-send-email-agust@denx.de> References: <1495045422-19183-1-git-send-email-agust@denx.de> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Joshua Clayton Add support for Altera cyclone V FPGA connected to an spi port to the evi devicetree file Signed-off-by: Joshua Clayton --- Changes in v10: - none arch/arm/boot/dts/imx6q-evi.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts index fd2220a..746ab07 100644 --- a/arch/arm/boot/dts/imx6q-evi.dts +++ b/arch/arm/boot/dts/imx6q-evi.dts @@ -94,6 +94,15 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>; status = "okay"; + + fpga_spi: cyclonespi@0 { + compatible = "altr,fpga-passive-serial"; + spi-max-frequency = <20000000>; + reg = <0>; + pinctrl-0 = <&pinctrl_fpgaspi>; + nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + }; }; &ecspi3 { @@ -319,6 +328,13 @@ >; }; + pinctrl_fpgaspi: fpgaspigrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + >; + }; + pinctrl_gpminand: gpminandgrp { fsl,pins = < MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 -- 2.7.4