From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756739AbdEUDo1 (ORCPT ); Sat, 20 May 2017 23:44:27 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:1798 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1756654AbdEUDn4 (ORCPT ); Sat, 20 May 2017 23:43:56 -0400 From: Ryder Lee To: Kishon Vijay Abraham I , Rob Herring CC: , , , , Ryder Lee Subject: [PATCH v2 2/2] dt-bindings: phy: Add documentation for Mediatek PCIe PHY Date: Sun, 21 May 2017 11:43:12 +0800 Message-ID: <1495338192-9423-3-git-send-email-ryder.lee@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495338192-9423-1-git-send-email-ryder.lee@mediatek.com> References: <1495338192-9423-1-git-send-email-ryder.lee@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add documentation for PCIe PHY available in MT7623 series SoCs. Signed-off-by: Ryder Lee Acked-by: Rob Herring --- .../devicetree/bindings/phy/phy-mt7623-pcie.txt | 63 ++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-mt7623-pcie.txt diff --git a/Documentation/devicetree/bindings/phy/phy-mt7623-pcie.txt b/Documentation/devicetree/bindings/phy/phy-mt7623-pcie.txt new file mode 100644 index 0000000..6fefac5 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-mt7623-pcie.txt @@ -0,0 +1,63 @@ +Mediatek MT7623 PCIe PHY +----------------------- + +Required properties: + - compatible: Should contain "mediatek,mt7623-pcie-phy". + - reg: Base address and length of the registers. + - clocks: Must contain an entry in clock-names. + See ../clocks/clock-bindings.txt for details. + - clock-names: Must be "pciephya_ref" + - #phy-cells: Must be 0. + +Optional properties: + - mediatek,phy-switch: A phandle to the system controller, used to + switch the PHY on PCIe port2 which is shared with USB u3phy2. + +Example: + + pcie0_phy: pcie-phy@1a149000 { + compatible = "mediatek,mt7623-pcie-phy"; + reg = <0 0x1a149000 0 0x1000>; + clocks = <&clk26m>; + clock-names = "pciephya_ref"; + #phy-cells = <0>; + }; + + pcie1_phy: pcie-phy@1a14a000 { + compatible = "mediatek,mt7623-pcie-phy"; + reg = <0 0x1a14a000 0 0x1000>; + clocks = <&clk26m>; + clock-names = "pciephya_ref"; + #phy-cells = <0>; + }; + + pcie2_phy: pcie-phy@1a244000 { + compatible = "mediatek,mt7623-pcie-phy"; + reg = <0 0x1a244000 0 0x1000>; + clocks = <&clk26m>; + clock-names = "pciephya_ref"; + #phy-cells = <0>; + + mediatek,phy-switch = <&hifsys>; + }; + +Specifying phy control of devices +--------------------------------- + +Device nodes should specify the configuration required in their "phys" +property, containing a phandle to the phy node and phy-names. + +Example: + +#include + +pcie: pcie@1a140000 { + ... + pcie@0,0 { + ... + phys = <&pcie0_phy>; + phy-names = "pcie-phy0"; + } + ... +}; + -- 1.9.1