From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423622AbdEYLUW (ORCPT ); Thu, 25 May 2017 07:20:22 -0400 Received: from esa4.microchip.iphmx.com ([68.232.154.123]:56093 "EHLO esa4.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1423369AbdEYLUS (ORCPT ); Thu, 25 May 2017 07:20:18 -0400 X-IronPort-AV: E=Sophos;i="5.38,391,1491289200"; d="scan'208";a="3109122" From: Eugen Hristev To: , , , , , , , , CC: Subject: [PATCH v3 3/4] ARM: dts: at91: sama5d2: add ADC hw trigger Date: Thu, 25 May 2017 14:17:13 +0300 Message-ID: <1495711034-28410-4-git-send-email-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495711034-28410-1-git-send-email-eugen.hristev@microchip.com> References: <1495711034-28410-1-git-send-email-eugen.hristev@microchip.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add ADTRG hardware pin possible edge types as nodes and default edge as property to the ADC Signed-off-by: Eugen Hristev --- arch/arm/boot/dts/sama5d2.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 8067c71..a06ca8d 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -1267,7 +1267,18 @@ atmel,min-sample-rate-hz = <200000>; atmel,max-sample-rate-hz = <20000000>; atmel,startup-time-ms = <4>; + atmel,trigger-edge-type = <&external_rising>; status = "disabled"; + + /* possible edge type for ADTRG trigger pin */ + adtrg: adtrg { + external_rising: external_rising { + }; + external_falling: external_falling { + }; + external_any: external_any { + }; + }; }; pioA: pinctrl@fc038000 { -- 2.7.4