From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750896AbdE3Eew (ORCPT ); Tue, 30 May 2017 00:34:52 -0400 Received: from ms.tdt.de ([195.243.126.94]:56182 "EHLO mail.dev.tdt.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750720AbdE3Eev (ORCPT ); Tue, 30 May 2017 00:34:51 -0400 From: Martin Schiller To: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Cc: john@phrozen.org, ralf@linux-mips.org, hauke@hauke-m.de, arnd@arndb.de, nbd@nbd.name, Martin Schiller Subject: [PATCH] MIPS: Lantiq: Fix ASC0/ASC1 clocks Date: Tue, 30 May 2017 06:34:34 +0200 Message-Id: <1496118874-4251-1-git-send-email-ms@dev.tdt.de> X-Mailer: git-send-email 2.1.4 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ASC1 is available on every Lantiq SoC (also AmazonSE) and should be enabled like the other generic xway clocks instead of ASC0, which is only available for AR9 and Danube. Signed-off-by: Martin Schiller --- arch/mips/lantiq/xway/sysctrl.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index 95bec46..cd6dbea 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -484,9 +484,9 @@ void __init ltq_soc_init(void) /* add our generic xway clocks */ clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI); - clkdev_add_pmu("1e100400.serial", NULL, 0, 0, PMU_ASC0); clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT); clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP); + clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1); clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA); clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI); clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU); @@ -501,7 +501,6 @@ void __init ltq_soc_init(void) } if (!of_machine_is_compatible("lantiq,ase")) { - clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1); clkdev_add_pci(); } -- 2.1.4