From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, mathieu.poirier@linaro.org,
Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH 10/12] coresight tmc: Support for save-restore in ETR
Date: Mon, 12 Jun 2017 15:36:49 +0100 [thread overview]
Message-ID: <1497278211-5001-11-git-send-email-suzuki.poulose@arm.com> (raw)
In-Reply-To: <1497278211-5001-1-git-send-email-suzuki.poulose@arm.com>
The Coresight SoC 600 TMC ETR supports save-restore feature,
where the values of the RRP/RWP and STS.Full are retained
when it leaves the Disabled state. Hence, we must program the
RRP/RWP and STS.Full to a proper value. For now, set the RRP/RWP
to the base address of the buffer and clear the STS.Full register.
This can be later exploited for proper save-restore of ETR
trace contexts (e.g, perf).
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 13 ++++++++++++-
drivers/hwtracing/coresight/coresight-tmc.h | 8 ++++++++
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index ff11b92..7294fb7 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -22,7 +22,7 @@
static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
{
- u32 axictl;
+ u32 axictl, sts;
/* Zero out the memory to help with debug */
memset(drvdata->vaddr, 0, drvdata->size);
@@ -45,6 +45,17 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
TMC_AXICTL_PROT_CTL_B1;
writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
tmc_write_dba(drvdata, drvdata->paddr);
+ /*
+ * If the TMC pointers must be programmed before the session,
+ * we have to set it properly (i.e, RRP/RWP to base address and
+ * STS to "not full").
+ */
+ if (tmc_has_cap(drvdata, TMC_CAP_ETR_SAVE_RESTORE)) {
+ tmc_write_rrp(drvdata, drvdata->paddr);
+ tmc_write_rwp(drvdata, drvdata->paddr);
+ sts = readl_relaxed(drvdata->base + TMC_STS) & ~TMC_STS_FULL;
+ writel_relaxed(sts, drvdata->base + TMC_STS);
+ }
writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 87e4561..d5ef51e 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -90,6 +90,14 @@ enum tmc_mem_intf_width {
};
#define TMC_CAP_ETR_SG_UNIT (1U << 0)
+/*
+ * TMC_CAP_ETR_SAVE_RESTORE - Values of RRP/RWP/STS.Full are
+ * retained when TMC leaves Disabled state, allowing us to continue
+ * the tracing from a point where we stopped. This also implies that
+ * the RRP/RWP/STS.Full should always be programmed to the correct
+ * value.
+ */
+#define TMC_CAP_ETR_SAVE_RESTORE (1U << 1)
/**
* struct tmc_cap - Describes the capabilities of the TMC.
--
2.7.4
next prev parent reply other threads:[~2017-06-12 14:38 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-12 14:36 [PATCH 00/12] coresight: Support for ARM Coresight SoC-600 Suzuki K Poulose
2017-06-12 14:36 ` [PATCH 01/12] coresight replicator: Cleanup programmable replicator naming Suzuki K Poulose
2017-06-13 16:55 ` Mathieu Poirier
2017-06-13 17:56 ` Suzuki K Poulose
2017-06-18 14:04 ` Rob Herring
2017-06-20 16:44 ` Mathieu Poirier
2017-06-22 3:21 ` Rob Herring
2017-06-12 14:36 ` [PATCH 02/12] arm64: dts: juno: Use the new coresight replicator string Suzuki K Poulose
2017-06-12 14:36 ` [PATCH 03/12] coresight: Extend the PIDR mask to cover relevant bits in PIDR2 Suzuki K Poulose
2017-06-13 17:53 ` Mathieu Poirier
2017-06-13 17:55 ` Suzuki K Poulose
2017-06-13 19:06 ` Mathieu Poirier
2017-06-12 14:36 ` [PATCH 04/12] coresight: Add support for reading 64bit registers Suzuki K Poulose
2017-06-13 17:45 ` Mathieu Poirier
2017-06-13 17:57 ` Suzuki K Poulose
2017-06-12 14:36 ` [PATCH 05/12] coresight tmc: Add helpers for accessing " Suzuki K Poulose
2017-06-14 17:49 ` Mathieu Poirier
2017-06-15 10:13 ` Suzuki K Poulose
2017-06-15 13:29 ` Mike Leach
2017-06-15 14:24 ` Mathieu Poirier
2017-06-12 14:36 ` [PATCH 06/12] coresight tmc: Expose DBA and AXICTL Suzuki K Poulose
2017-06-14 17:50 ` Mathieu Poirier
2017-06-15 10:19 ` Suzuki K Poulose
2017-06-12 14:36 ` [PATCH 07/12] coresight replicator: Expose replicator management registers Suzuki K Poulose
2017-06-14 17:54 ` Mathieu Poirier
2017-06-15 10:23 ` Suzuki K Poulose
2017-06-12 14:36 ` [PATCH 08/12] coresight tmc: Handle configuration types properly Suzuki K Poulose
2017-06-14 17:59 ` Mathieu Poirier
2017-06-15 10:25 ` Suzuki K Poulose
2017-06-15 14:33 ` Mathieu Poirier
2017-06-12 14:36 ` [PATCH 09/12] coresight tmc: Add capability information Suzuki K Poulose
2017-06-14 18:22 ` Mathieu Poirier
2017-06-15 10:30 ` Suzuki K Poulose
2017-06-15 14:37 ` Mathieu Poirier
2017-06-12 14:36 ` Suzuki K Poulose [this message]
2017-06-12 14:36 ` [PATCH 11/12] coresight tmc: Add support for Coresight SoC 600 TMC Suzuki K Poulose
2017-06-14 18:25 ` Mathieu Poirier
2017-06-15 10:31 ` Suzuki K Poulose
2017-06-12 14:36 ` [PATCH 12/12] coresight: Add support for Coresight SoC 600 components Suzuki K Poulose
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