From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752800AbdGFIZN (ORCPT ); Thu, 6 Jul 2017 04:25:13 -0400 Received: from regular1.263xmail.com ([211.150.99.130]:39874 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751923AbdGFIZI (ORCPT ); Thu, 6 Jul 2017 04:25:08 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-RL-SENDER: zhangqing@rock-chips.com X-FST-TO: mturquette@baylibre.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: zhangqing@rock-chips.com X-UNIQUE-TAG: <33346923cdcc362cda5f0845523b54d6> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: Elaine Zhang To: mturquette@baylibre.com, sboyd@codeaurora.org, heiko@sntech.de Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, huangtao@rock-chips.com, cl@rock-chips.com, xxx@rock-chips.com, xf@rock-chips.com, Elaine Zhang Subject: [PATCH v1] clk: fractional-divider: fix up the fractional clk's jitter Date: Thu, 6 Jul 2017 16:28:34 +0800 Message-Id: <1499329714-24119-1-git-send-email-zhangqing@rock-chips.com> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org fractional divider must set that denominator is 20 times larger than numerator to generate precise clock frequency. Otherwise the CLK jitter is very big, poor quality of the clock signal. RK document description: 3.1.9 Fractional divider usage To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by fractional divider. Generally you must set that denominator is 20 times larger than numerator to generate precise clock frequency. So the fractional divider applies only to generate low frequency clock like I2S, UART. Signed-off-by: Elaine Zhang --- drivers/clk/clk-fractional-divider.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index aab904618eb6..1c29d6f5ffd8 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -56,11 +56,24 @@ static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long scale; unsigned long m, n; u64 ret; + struct clk_hw *p_parent; + unsigned long p_rate, p_parent_rate; if (!rate || rate >= *parent_rate) return *parent_rate; /* + * fractional divider must set that denominator is 20 times larger than + * numerator to generate precise clock frequency. + */ + p_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); + if ((rate * 20 > p_rate) && (p_rate % rate != 0)) { + p_parent = clk_hw_get_parent(clk_hw_get_parent(hw)); + p_parent_rate = clk_hw_get_rate(p_parent); + *parent_rate = p_parent_rate; + } + + /* * Get rate closer to *parent_rate to guarantee there is no overflow * for m and n. In the result it will be the nearest rate left shifted * by (scale - fd->nwidth) bits. -- 1.9.1