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([2600:8803:e7e4:500:b5c0:1844:fb75:2a91]) by smtp.gmail.com with ESMTPSA id 5614622812f47-443df722e5csm2662753b6e.24.2025.10.21.07.59.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Oct 2025 07:59:23 -0700 (PDT) Message-ID: <14ae0769-341b-4325-b925-7bba6d57bbdf@baylibre.com> Date: Tue, 21 Oct 2025 09:59:22 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/6] dt-bindings: spi: Add spi-buses property To: Rob Herring Cc: Mark Brown , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?UTF-8?Q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko , Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org References: <20251014-spi-add-multi-bus-support-v1-0-2098c12d6f5f@baylibre.com> <20251014-spi-add-multi-bus-support-v1-1-2098c12d6f5f@baylibre.com> <20251021142129.GA34073-robh@kernel.org> Content-Language: en-US From: David Lechner In-Reply-To: <20251021142129.GA34073-robh@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 10/21/25 9:21 AM, Rob Herring wrote: > On Tue, Oct 14, 2025 at 05:02:11PM -0500, David Lechner wrote: >> Add a spi-buses property to the spi-peripheral-props binding to allow >> specifying the SPI data bus or buses that a peripheral is connected to >> in cases where the SPI controller has more than one physical SPI data >> bus. > > Is there a reason why spi-rx-bus-width property doesn't work for you? > The only thing I see would be you need to define the order of the pins > like "data-lanes" property. > > Rob Because we can have both at the same time. In one of the other threads, we talked about the AD4630 ADC that will require this since it has 2 data buses each with a width of 4 (total of 8 lines). See: https://lore.kernel.org/linux-iio/ad929fe5-be03-4628-b95a-5c3523bae0c8@baylibre.com/