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Sat, 06 Sep 2025 13:56:19 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGSFjvOo/qTGxHXp3wiVQKj7HoGwmGtWzfJpDenuCSbN2DKNJDPXY8f/qc5OOKz5fQQXodCEg== X-Received: by 2002:a05:6a20:734c:b0:24a:69c5:e9d9 with SMTP id adf61e73a8af0-2534557a858mr4403357637.39.1757192178483; Sat, 06 Sep 2025 13:56:18 -0700 (PDT) Received: from [192.168.1.5] ([106.222.231.120]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7727822817asm12558174b3a.98.2025.09.06.13.56.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 06 Sep 2025 13:56:18 -0700 (PDT) Message-ID: <14b5db9f-8b31-4baa-a03d-12112425fbbe@oss.qualcomm.com> Date: Sun, 7 Sep 2025 02:26:09 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/6] arm64: dts: qcom: sa8775p: Add gpu and gmu nodes To: Konrad Dybcio , Dmitry Baryshkov Cc: Sean Paul , Konrad Dybcio , Abhinav Kumar , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Connor Abbott , Srinivas Kandagatla , Rob Clark , Dmitry Baryshkov , Gaurav Kohli , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Puranam V G Tejaswi References: <20250822-a663-gpu-support-v4-0-97d26bb2144e@oss.qualcomm.com> <20250822-a663-gpu-support-v4-3-97d26bb2144e@oss.qualcomm.com> From: Akhil P Oommen Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: XIzWqyC9-p7kym154zXuRhNr5pjxMGkV X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAyNyBTYWx0ZWRfX+8mC4+z2iNgh TzgaO1hfcNxzI3VLR6AcLC5Rcqn0Jm35OaVRUbpwkLVHw1cTMrD21K6XJnwGZFseFB7mgrqXLWE FaOV5Weev8SPLkGJFlUegPyyUIRv1FikIXNzZ/65F49dY0TcRw+gpzQQ3nsD0PsNWJALVZXm2pN Pm+H2lzFc207z2ZP2xHACCKFYBM4Qh3Z7qJeWPLWmvXlAiAxcsWczp/y7xZuyFXN4ljjB3kdFqA nBpsrqnrSOT4XCjYdCWJdCohFn26n5Oqo59bHJcDqcbrvZBTdXu7iL4NLQshkFkecvbHb+uCN9N 22/Ui3JM+oMDWNqaTPOwq/DNybGxnaGI0YalVlvbfdlJXDYUf0PfygRTf8GeLLG8/zOzHXygcsz tXcqdJH5 X-Authority-Analysis: v=2.4 cv=cYXSrmDM c=1 sm=1 tr=0 ts=68bc9ff4 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=LaKoERy2ZarllCCVqnwusw==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=fXDYdZQTyQKxOPRIeewA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: XIzWqyC9-p7kym154zXuRhNr5pjxMGkV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-06_07,2025-09-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 impostorscore=0 clxscore=1015 malwarescore=0 phishscore=0 spamscore=0 suspectscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060027 On 9/3/2025 8:44 PM, Konrad Dybcio wrote: > On 9/3/25 4:00 PM, Dmitry Baryshkov wrote: >> On Wed, Sep 03, 2025 at 03:36:34PM +0200, Konrad Dybcio wrote: >>> On 9/3/25 2:39 PM, Dmitry Baryshkov wrote: >>>> On Wed, Sep 03, 2025 at 02:26:30PM +0200, Konrad Dybcio wrote: >>>>> On 8/21/25 8:55 PM, Akhil P Oommen wrote: >>>>>> From: Puranam V G Tejaswi >>>>>> >>>>>> Add gpu and gmu nodes for sa8775p chipset. As of now all >>>>>> SKUs have the same GPU fmax, so there is no requirement of >>>>>> speed bin support. >>>>>> >>>>>> Signed-off-by: Puranam V G Tejaswi >>>>>> Signed-off-by: Akhil P Oommen >>>>>> Reviewed-by: Dmitry Baryshkov >>>>>> --- >>>>>> arch/arm64/boot/dts/qcom/lemans.dtsi | 116 +++++++++++++++++++++++++++++++++++ >>>>>> 1 file changed, 116 insertions(+) >>>>>> >>>>>> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi >>>>>> index 8ceb59742a9fc6562b2c38731ddabe3a549f7f35..8eac8d4719db9230105ad93ac22287850b6b007c 100644 >>>>>> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi >>>>>> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi >>>>>> @@ -1097,6 +1097,18 @@ ipcc: mailbox@408000 { >>>>>> #mbox-cells = <2>; >>>>>> }; >>>>>> >>>>>> + qfprom: efuse@784000 { >>>>>> + compatible = "qcom,sa8775p-qfprom", "qcom,qfprom"; >>>>>> + reg = <0x0 0x00784000 0x0 0x2410>; >>>>> >>>>> len = 0x3000 >>>>> >>>>> [...] >>>>> >>>>>> + gmu: gmu@3d6a000 { >>>>>> + compatible = "qcom,adreno-gmu-663.0", "qcom,adreno-gmu"; >>>>>> + reg = <0x0 0x03d6a000 0x0 0x34000>, >>>>> >>>>> This bleeds into GPU_CC, len should be 0x26000 >>>> >>>> gpucc is in the middle of GMU, see other platforms. >>> >>> This is not the case here >> >> Why? I think GPU CC is a part of the GMU by design: GMU accesses GPU CC >> registers directly from the firmware. > > Correct, however this is only a similarly sounding argument - the DT > describes the hardware from the main Arm cluster POV. The GMU Cortex-M > core has its own address map etc. We have been keeping GPUCC region in the GMU's reg range in all chipsets for the purpose of coredump. Can we leave this as is until we have a mechanism to dump these into gpu coredump (via gpucc driver??)? I recall you proposed something similar sometime back. -Akhil > > Konrad